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| PIC16C432 Data Sheet OTP 8-Bit CMOS MCU with LIN Transceiver 2002 Microchip Technology Inc. Preliminary DS41140B Note the following details of the code protection feature on PICmicro(R) MCUs. * * * The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable". Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product. * * * If you have any further questions about this matter, please contact the local sales office nearest to you. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, KEELOQ, MPLAB, PIC, PICmicro, PICSTART and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. DS41140B - page ii Preliminary 2002 Microchip Technology Inc. PIC16C432 OTP 8-Bit CMOS MCU with LIN Transceiver Devices included in this Data Sheet: * PIC16C432 PIN DIAGRAM Ceramic DIP, SSOP, PDIP LIN RA2/AN2/VREF RA3/AN3 RA4/T0CKI MCLR/VPP VSS RB0/INT RB1 RB2 RB3 1 2 3 4 PIC16C432 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VBAT BACT VSS RA0/AN0 RA0/AN0 OSC1/CLKIN OSC1/CLKIN OSC2/CLKOUT OSC2/CLKVDD OUT RB7 VDD RB6 RB7 RB5 RB4 RB6 High Performance RISC CPU: * Only 35 instructions to learn * All single cycle instructions (200 ns), except for program branches which are two-cycle * Operating speed: - DC - 20 MHz clock input - DC - 200 ns instruction cycle Device PIC16C432 * * * * Program Memory 2K x 14 RAM Data Memory 128 x 8 Interrupt capability 16 special function hardware registers 8-level deep hardware stack Direct, Indirect and Relative Addressing modes Special Microcontroller Features: * In-Circuit Serial Programming (ICSPTM) (via two pins) * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Brown-out Reset * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable code protection * Power saving SLEEP mode * Selectable oscillator options * Four user programmable ID locations Peripheral Features: * 12 I/O pins with individual direction control * High current sink/source for direct LED drive * Analog comparator module with: - Two analog comparators - Programmable on-chip voltage reference (VREF) module - Programmable input multiplexing from device inputs and internal voltage reference - Comparator outputs can be output signals * Timer0: 8-bit timer/counter with 8-bit programmable prescaler * Integrated LIN Transceiver * Wake-up on bus activity * 12V battery operation for Transceiver * Thermal shutdown for Transceiver * Ground loss protection CMOS Technology: * Low power, high speed CMOS EPROM/HV-CMOS technology * Fully static design * Operating voltage range - 4.5V to 5.5V * Industrial and extended temperature range 2002 Microchip Technology Inc. Preliminary DS41140B-page 1 PIC16C432 Table of Contents 1.0 General Description...................................................................................................................................................................... 3 2.0 PIC16C432 Device Varieties ........................................................................................................................................................ 5 3.0 Memory Organization ................................................................................................................................................................... 7 4.0 I/O Ports ..................................................................................................................................................................................... 17 5.0 LIN Transceiver .......................................................................................................................................................................... 23 6.0 Timer0 Module ........................................................................................................................................................................... 27 7.0 Comparator Module.................................................................................................................................................................... 33 8.0 Voltage Reference Module......................................................................................................................................................... 41 9.0 Special Features of the CPU ...................................................................................................................................................... 43 10.0 Instruction Set Summary ............................................................................................................................................................ 59 11.0 Development Support................................................................................................................................................................. 73 12.0 Electrical Specifications.............................................................................................................................................................. 79 13.0 DC and AC Characteristics Graphs and Tables ......................................................................................................................... 91 14.0 Packaging Information................................................................................................................................................................ 93 Appendix A: Code for LIN Communication ...................................................................................................................................... 97 Index: .................................................................................................................................................................................................. 99 On-Line Support................................................................................................................................................................................. 101 Systems Information and Upgrade Hot Line ...................................................................................................................................... 101 Reader Response .............................................................................................................................................................................. 102 Product Identification System............................................................................................................................................................. 103 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS41140B-page 2 Preliminary 2002 Microchip Technology Inc. PIC16C432 1.0 GENERAL DESCRIPTION The PIC16C432 is a 20-pin EPROM-based member of the versatile PICmicro(R) family of low cost, high performance, CMOS, fully-static, 8-bit microcontrollers with an integrated LIN transceiver. The LIN physical layer is implemented in hardware with a voltage range from 0V to 18V, with a 40V transient capability. The LIN protocol is to be implemented in firmware, which enables flexibility with future revisions of the LIN protocol. All PICmicro microcontrollers employ an advanced RISC architecture. The PIC16C432 device has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with separate 8-bit wide data. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. PIC16C432 microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. The PIC16C432 has 12 I/O pins and an 8-bit timer/ counter with an 8-bit programmable prescaler. In addition, the PIC16C432 adds two analog comparators with a programmable on-chip voltage reference module. The comparator module is ideally suited for applications requiring a low cost analog interface (e.g., battery chargers, threshold detectors, white goods controllers, etc.). PIC16C432 devices have special features to reduce external components, thus reducing system cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) mode offers power savings. The user can wake-up the chip from SLEEP through several external and internal interrupts and RESET. (R) A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lockup. A UV erasable CERDIP packaged version is ideal for code development, while the cost effective One-TimeProgrammable (OTP) version is suitable for production in any volume. A simplified block diagram of the PIC16C432 is shown in Figure 4-1. The PIC16C432 series fits perfectly in automotive and industrial applications, which require LIN as a communication platform. The EPROM technology makes customization of application programs (detection levels, pulse generation, timers, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low cost, low power, high performance, ease of use and I/O flexibility make the PIC16C432 very versatile. 1.1 Development Support The PIC16C432 family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low cost development programmer and a full-featured programmer. A "C" compiler is also available. 2002 Microchip Technology Inc. Preliminary DS41140B-page 3 PIC16C432 NOTES: DS41140B-page 4 Preliminary 2002 Microchip Technology Inc. PIC16C432 2.0 PIC16C432 DEVICE VARIETIES 2.3 A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C432 Product Identification System section at the end of this data sheet. Quick-Turn-Programming (QTP) Devices 2.1 UV Erasable Devices The UV erasable version, offered in the CERDIP package is optimal for prototype development and pilot programs. This version can be erased and reprogrammed to any of the oscillator modes. Microchip's PRO MATE programmers support programming of the PIC16C432. Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices, but with all EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your Microchip Technology sales office for more details. 2.4 Serialized Quick-Turn-Programming (SQTPSM) Devices 2.2 One-Time-Programmable (OTP) Devices The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. In addition to the program memory, the configuration bits must also be programmed. Microchip offers a unique programming service where a few user defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry code, password or ID number. 2002 Microchip Technology Inc. Preliminary DS41140B-page 5 PIC16C432 NOTES: DS41140B-page 6 Preliminary 2002 Microchip Technology Inc. PIC16C432 3.0 3.1 MEMORY ORGANIZATION Program Memory Organization 3.2 Data Memory Organization The PIC16C432 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 2K x 14 (0000h - 07FFh) are implemented for the PIC16C432. Accessing a location above these boundaries will cause a wrap-around within the first 2K x 14 space. The RESET Vector is at 0000h and the Interrupt Vector is at 0004h (Figure 3-1). FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR THE PIC16C432 PC<12:0> The data memory (Figure 3-2) is partitioned into two Banks, which contain the General Purpose Registers and the Special Function Registers. Bank 0 is selected when the RP0 bit is cleared. Bank 1 is selected when the RP0 bit (STATUS <5>) is set. The Special Function Registers are located in the first 32 locations of each Bank. Register locations 20-7Fh (Bank 0) and A0-BFh (Bank 1) are General Purpose Registers implemented as static RAM. Some special purpose registers are mapped in Bank 1. In the microcontroller, address space F0h-FFh (Bank 1) is mapped to 70-7Fh (Bank 0) as common RAM. 3.2.1 GENERAL PURPOSE REGISTER FILE CALL, RETURN RETFIE, RETLW 13 Stack Level 1 Stack Level 2 Stack Level 8 RESET Vector 000h The register file is organized as 128 x 8 in the PIC16C432. Each is accessed either directly or indirectly through the File Select Register FSR (Section 3.4). Interrupt Vector 0004h 0005h On-chip Program Memory 07FFh 0800h 1FFFh 2002 Microchip Technology Inc. Preliminary DS41140B-page 7 PIC16C432 FIGURE 3-2: File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h INDF(1) TMR0 PCL STATUS FSR PORTA PORTB INDF(1) OPTION PCL STATUS FSR TRISA TRISB DATA MEMORY MAP FOR THE PIC16C432 File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h 3.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (Table 3-1). These registers are static RAM. The special registers can be classified into two sets (core and peripheral). The Special Function Registers associated with the "core" functions are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. PCLATH INTCON PIR1 PCLATH INTCON PIE1 PCON LININTF CMCON General Purpose Register VRCON General Purpose Register BFh C0h F0h FFh Accesses 70h-7Fh 7Fh Bank 0 Bank 1 Unimplemented data memory locations,read as '0'. Note 1: Not a physical register. DS41140B-page 8 Preliminary 2002 Microchip Technology Inc. PIC16C432 TABLE 3-1: Address Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch INDF TMR0 PCL STATUS FSR PORTA PORTB -- -- -- PCLATH INTCON PIR1 Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module's Register Program Counter's (PC) Least Significant Byte IRP(2) RP1(2) RP0 TO PD Z DC C xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx RA3 RB3 RA2 RB2 LINRX RB1 RA0 RB0 ---x 0000 xxxx xxxx -- -- -- -- T0IE -- Write buffer for upper 5 bits of program counter INTE -- RBIE -- T0IF -- INTF -- RBIF -- ---0 0000 0000 000x -0-- ----- -- -- CIS CM2 CM1 CM0 00-- 0000 16 27 15 10 16 17 20 -- -- -- 15 12 13 -- 33 SPECIAL REGISTERS FOR THE PIC16C432 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other RESETS(1) Indirect data memory address pointer -- RB7 -- RB6 -- RB5 RA4 RB4 Unimplemented Unimplemented Unimplemented -- GIE -- -- PEIE CMIF 0Dh-1Eh -- 1Fh Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh-9Eh 90h 9Fh INDF OPTION_REG PCL STATUS FSR TRISA TRISB -- -- -- PCLATH INTCON PIE1 -- PCON -- LININTF VRCON CMCON Unimplemented C2OUT C1OUT Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 xxxx xxxx 1111 1111 0000 0000 16 11 15 10 16 17 20 -- -- -- 15 12 13 -- 14 -- 23 41 Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC TLINRX(3) TRISB1 C 0001 1xxx xxxx xxxx Indirect data memory address pointer -- TRISB7 -- TRISB6 -- TRISB5 TRISA4 TRISB4 TRISA3 TRISB3 TRISA2 TRISB2 TRISA0 TRISB0 ---1 1111 1111 1111 -- -- -- Unimplemented Unimplemented Unimplemented -- GIE -- -- PEIE CMIE -- T0IE -- Write buffer for upper 5 bits of program counter INTE -- RBIE -- T0IF -- INTF -- RBIF -- ---0 0000 0000 000x -0-- ----- Unimplemented -- -- -- -- -- -- POR BOD ---- --0x -- Unimplemented -- VREN -- VROE -- VRR -- -- -- VR3 LINTX VR2 -- VR1 LINVDD VR0 ---- -1-1 000- 0000 Legend: -- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non power-up) RESETS include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal operation. 2: IRP & RPI bits are reserved; always maintain these bits clear. 3: TLINRX must set to `1' at all times. 2002 Microchip Technology Inc. Preliminary DS41140B-page 9 PIC16C432 3.2.2.1 STATUS Register The STATUS register, shown in Register 3-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000uu1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any STATUS bit. For other instructions, not affecting any STATUS bits, see the "Instruction Set Summary". Note 1: The IRP and RP1 bits (STATUS<7:6>) are not used by the PIC16C432 and should be programmed as '0'. Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products. 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. REGISTER 3-1: STATUS REGISTER (ADDRESS 03h OR 83h) Reserved IRP bit7 Reserved RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0 bit 7 bit 6-5 IRP: The IRP bit is reserved on the PIC16C432, always maintain this bit clear RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes. The RP1 bit is reserved, always maintain this bit clear. TO: Timeout bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT timeout occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: bit 4 bit 3 bit 2 Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred bit 0 Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown DS41140B-page 10 Preliminary 2002 Microchip Technology Inc. PIC16C432 3.2.2.2 OPTION Register Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT (PSA = 1). The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external RB0/INT interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 3-2: OPTION REGISTER (ADDRESS 81h) R/W-1 RBPU bit7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 bit 6 bit 5 bit 4 bit 3 bit 2-0 Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2002 Microchip Technology Inc. Preliminary DS41140B-page 11 PIC16C432 3.2.2.3 INTCON Register Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). The INTCON register is a readable and writable register which contains the various enable and flag bits for all interrupt sources, except the comparator module. See Section 3.2.2.4 and Section 3.2.2.5 for a description of the comparator enable and flag bits. REGISTER 3-3: INTCON REGISTER (ADDRESS 0Bh OR 8Bh) R/W-0 GIE bit7 R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit0 bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB<7:4> pins changed state (must be cleared in software) 0 = None of the RB<7:4> pins have changed state Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS41140B-page 12 Preliminary 2002 Microchip Technology Inc. PIC16C432 3.2.2.4 PIE1 Register This register contains the individual enable bit for the comparator interrupt. REGISTER 3-4: PIE1 REGISTER (ADDRESS 8CH) U-0 -- bit7 R/W-0 CMIE U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit0 bit 7 bit 6 Unimplemented: Read as '0' CMIE: Comparator Interrupt Flag bit 1 = Enables the Comparator interrupt 0 = Disables the Comparator interrupt Unimplemented: Read as '0' Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 5-0 3.2.2.5 PIR1 Register This register contains the individual flag bit for the comparator interrupt. Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 3-5: PIR1 REGISTER (ADDRESS 0Ch) U-0 -- bit7 R/W-0 CMIF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit0 bit 7 bit 6 Unimplemented: Read as '0' CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed 0 = Comparator input has not changed Unimplemented: Read as '0' Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 5-0 2002 Microchip Technology Inc. Preliminary DS41140B-page 13 PIC16C432 3.2.2.6 PCON Register The PCON register contains flag bits to differentiate between a Power-on Reset, an external MCLR Reset, WDT Reset or a Brown-out Reset. Note: BOD is unknown on Power-on Reset. It must then be set by the user and checked on subsequent RESETS to see if BOD is cleared, indicating a brown-out has occurred. The BOD status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (by programming BODEN bit in the configuration word). REGISTER 3-6: PCON REGISTER (ADDRESS 8Eh)) U-0 -- bit7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR R/W-0 BOD bit0 bit 7-2 bit 1 Unimplemented: Read as '0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOD: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 0 DS41140B-page 14 Preliminary 2002 Microchip Technology Inc. PIC16C432 3.3 PCL and PCLATH 3.3.2 STACK The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any RESET, the PC is cleared. Figure 3-3 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). The PIC16C432 family has an 8 level deep x 13-bit wide hardware stack (Figure 3-1 and Figure 3-1). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth PUSH overwrites the value that was stored from the first PUSH. The tenth PUSH overwrites the second PUSH (and so on). Note 1: There are no STATUS bits to indicate stack overflow or stack underflow conditions. 2: There are no instruction/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions, or the vectoring to an interrupt address. FIGURE 3-3: LOADING OF PC IN DIFFERENT SITUATIONS PCL 8 7 0 Instruction with PCL as Destination ALU result PCH 12 PC 5 PCLATH<4:0> 8 PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0 GOTO, CALL 3.3.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the Application Note, "Implementing a Table Read" (AN556). 2002 Microchip Technology Inc. Preliminary DS41140B-page 15 PIC16C432 3.4 Indirect Addressing, INDF and FSR Registers A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 3-1. The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a nooperation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 3-4. However, IRP is not used in the PIC16C432. EXAMPLE 3-1: movlw movwf NEXT clrf incf btfss goto CONTINUE: INDIRECT ADDRESSING 0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue FIGURE 3-4: DIRECT/INDIRECT ADDRESSING PIC16C432 Direct Addressing Indirect Addressing 0 IRP(1) 7 FSR Register 0 RP1 RP0 (1) 6 from opcode bank select location select bank select location select 00 00h 01 10 11 180h not used Data Memory 7Fh Bank 0 Bank 1 Bank 2 Bank 3 1FFh For memory map detail see Figure 3-2 and Figure 3-2. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. DS41140B-page 16 Preliminary 2002 Microchip Technology Inc. PIC16C432 4.0 I/O PORTS Note: The PIC16C432 parts have two ports, PORTA and PORTB. Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. On RESET, the TRISA register is set to all inputs. The digital inputs are disabled and the comparator inputs are forced to ground, to reduce excess current consumption. 4.1 PORTA and TRISA Registers PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. Port RA4 is multiplexed with the T0CKI clock input. All other RA port pins have Schmitt Trigger input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers), which can configure these pins as input or output. A '1' in the TRISA register puts the corresponding output driver in a Hi-impedance mode. A '0' in the TRISA register puts the contents of the output latch on the selected pin(s). Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. The PORTA pins are multiplexed with comparator and voltage reference functions. The operation of these pins are selected by control bits in the CMCON (Comparator Control Register) register and the VRCON (Voltage Reference Control Register) register. When selected as a comparator input, these pins will read as '0's. TRISA controls the direction of the RA pins, even when they are being used as comparator inputs. The user must make sure to keep the pins configured as inputs when using them as comparator inputs. The RA2 pin will also function as the output for the voltage reference. When in this mode, the VREF pin is a very high impedance output. The user must configure TRISA<2> bit as an input and use high impedance loads. In one of the comparator modes defined by the CMCON register, pins RA3 and RA4 become outputs of the comparators. The TRISA<4:3> bits must be cleared to enable outputs to use this function. EXAMPLE 4-1: CLRF MOVLW MOVWF BSF MOVLW MOVWF PORTA 0X07 CMCON STATUS, RP0 0x1F TRISA INITIALIZING PORTA ;Initialize PORTA by setting ;output data latches ;Turn comparators off and ;enable pins for I/O ;functions ;Select Bank1 ;Value used to initialize ;data direction ;Set RA<4:0> as inputs ;TRISA<7:5> are always ;read as '0'. FIGURE 4-1: Data Bus WR PORTA BLOCK DIAGRAM OF RA0 PINS Q VDD VDD Note 1: BACT pin is an output and must be left open if unused. D CK Q Data Latch D Q P WR TRISA N CK Q Vss Analog Input Mode Schmitt Trigger Input Buffer Q EN D TRIS Latch I/O Pin RD TRISA RD PORTA To Comparator 2002 Microchip Technology Inc. Preliminary DS41140B-page 17 PIC16C432 FIGURE 4-2: Data Bus WR PORTA BLOCK DIAGRAM OF RA2 PIN Q VDD VDD D CK Q P Data Latch D WR TRISA Q N CK Q Vss Analog Input Mode Schmitt Trigger Input Buffer RA2 Pin TRIS Latch RD TRISA Q D EN RD PORTA To Comparator VROE VREF FIGURE 4-3: Data Bus WR PORTA D BLOCK DIAGRAM OF RA3 PIN Comparator Mode = 110 Q Comparator Output VDD P VDD Q CK Data Latch D Q WR TRISA N CK Q Vss Analog Input Mode Schmitt Trigger Input Buffer Q D EN TRIS Latch RA3 Pin RD TRISA RD PORTA To Comparator DS41140B-page 18 Preliminary 2002 Microchip Technology Inc. PIC16C432 FIGURE 4-4: Data Bus WR PORTA D CK BLOCK DIAGRAM OF RA4 PIN Comparator Mode = 110 Q Comparator Output Q Q N CK Q Vss TRIS Latch RA4 Pin Data Latch D WR TRISA RD TRISA Q D EN RD PORTA Schmitt Trigger Input Buffer TMR0 Clock Input TABLE 4-1: Name RA0/AN0 LINRX RA2/AN2/VREF RA3/AN3 RA4/T0CKI PORTA FUNCTIONS Bit # bit0 bit1 bit2 bit3 bit4 Buffer Type ST ST ST ST ST Function Input/output or comparator input. LIN receive pin. Input/output or comparator input or VREF output. Input/output or comparator input/output. Input/output or external clock input for TMR0 or comparator output. Output is open drain type. Legend: ST = Schmitt Trigger input TABLE 4-2: Address 05h 85h 1Fh 9Fh Name PORTA TRISA SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 -- -- C2OUT VREN Bit 6 -- -- C1OUT VROE Bit 5 -- -- -- VRR Bit 4 RA4 TRISA4 -- -- Bit 3 RA3 TRISA3 CIS VR3 Bit 2 RA2 TRISA2 CM2 VR2 Bit 1 LINRX TLINRX(2) CM1 VR1 Bit 0 RA0 TRISA0 CM0 VR0 Value on: POR ---x 0000 ---1 1111 00-- 0000 000- 0000 Value on All Other RESETS ---u 0000 ---1 1111 00-- 0000 000- 0000 CMCON VRCON Legend: -- = Unimplemented locations, read as `0', x = unknown, u = unchanged Note 1: Shaded bits are not used by PORTA. 2: TLINRX must be set to `1' at all times. 2002 Microchip Technology Inc. Preliminary DS41140B-page 19 PIC16C432 4.2 PORTB and TRISB Registers PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. A '1' in the TRISB register puts the corresponding output driver in a High Impedance mode. A '0' in the TRISB register puts the contents of the output latch on the selected pin(s). Reading PORTB register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. Each of the PORTB pins has a weak internal pull-up (200 A typical). A single control bit can turn on all the pull-ups. This is done by clearing the RBPU (OPTION<7>) bit. The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on Power-on Reset. Four of PORTB's pins, RB<7:4>, have an interrupt-onchange feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB<7:4> pin configured as an output is excluded from the interrupt-onchange comparison). The input pins of RB<7:4> are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB<7:4> are OR'ed together to generate the RBIF interrupt (flag latched in INTCON<0>). This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF. A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. This interrupt-on-mismatch feature, together with software configurable pull-ups on these four pins, allow easy interface to a key pad and make it possible for wake-up on key depression. (See AN552, "Implementing Wake-up on Key Strokes".) Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. FIGURE 4-6: BLOCK DIAGRAM OF RB<3:0> PINS VDD FIGURE 4-5: BLOCK DIAGRAM OF RB<7:4> PINS VDD P Weak Pull-up RBPU(1) Data Latch D Q CK TRIS Latch D Q WR TRISB(1) CK P Weak Pull-up I/O pin Data Bus WR PORTB I/O pin RBPU(1) Data Latch D Q CK TRIS Latch D Q WR TRISB(1) CK TTL Input Buffer Data Bus WR PORTB TTL Input Buffer RD TRISB ST Buffer RD PORTB Q D EN RD TRISB Q RD PORTB Latch D RB0/INT EN Set RBIF ST Buffer Note 1: RD Port From other RB<7:4> pins Q D EN RD Port TRISB = 1 enables weak pull-up if RBPU = 0 (OPTION<7>). RB<7:6> in Serial Programming mode Note 1: TRISB = 1 enables weak pull-up if RBPU = 0 (OPTION<7>). DS41140B-page 20 Preliminary 2002 Microchip Technology Inc. PIC16C432 TABLE 4-3: Name RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 Legend: Note 1: 2: PORTB FUNCTIONS Bit # bit0 Buffer Type TTL/ST(1) Function Input/output or external interrupt input. Internal software programmable weak pull-up. bit1 TTL Input/output pin. Internal software programmable weak pull-up. bit2 TTL Input/output pin. Internal software programmable weak pull-up. bit3 TTL Input/output pin. Internal software programmable weak pull-up. bit4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. bit5 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable bit6 TTL/ST(2) weak pull-up. Serial programming clock pin. Input/output pin (with interrupt-on-change). Internal software programmable bit7 TTL/ST(2) weak pull-up. Serial programming data pin. ST = Schmitt Trigger, TTL = TTL input This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in Serial Programming mode. TABLE 4-4: Address 06h 86h 81h Name PORTB TRISB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 RB7 TRISB7 RBPU Bit 6 RB6 TRISB6 INTEDG Bit 5 RB5 Bit 4 RB4 Bit 3 RB3 Bit 2 RB2 Bit 1 RB1 Bit 0 RB0 Value on: POR xxxx xxxx Value on All Other RESETS uuuu uuuu 1111 1111 1111 1111 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 T0CS T0SE PSA PS2 PS1 PS0 1111 1111 OPTION Legend: u = unchanged, x = unknown Note 1: Shaded bits are not used by PORTB. 2002 Microchip Technology Inc. Preliminary DS41140B-page 21 PIC16C432 4.3 4.3.1 I/O Programming Considerations BI-DIRECTIONAL I/O PORTS EXAMPLE 4-2: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT PORTB<7:4> Inputs PORTB<3:0> Outputs Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (i.e., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and re-written to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the Input mode, no problem occurs. However, if bit0 is switched into Output mode later on, the content of the data latch may now be unknown. Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read-modify-write instructions (i.e., BCF, BSF, etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. Example 4-2 shows the effect of two sequential readmodify-write instructions (i.e., BCF, BSF, etc.) on an I/O port. A pin actively outputting a Low or High should not be driven from external devices at the same time, in order to change the level on this pin ("wired-or", "wired-and"). The resulting high output currents may damage the chip. ; Initial PORT settings: ; PORTB<7:6> have external pull-up and are not connected ; to other circuitry ; ; ; BCF PORTB, 7 BCF PORTB, 6 BSF STATUS, RP0 BCF TRISB, 7 BCF TRISB, 6 ; ; NOTE: that the user may have expected the pin values to ; be 00pp pppp. The 2nd BCF caused RB7 to be latched as ; the pin value (High). PORT latch -----------------PORT pins ---------------- ; 01pp pppp ;10pp pppp ; ; 10pp pppp ; 10pp pppp 11pp pppp 11pp pppp 11pp pppp 10pp pppp 4.3.2 SUCCESSIVE OPERATIONS ON I/O PORTS The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 47). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction causes that file to be read into the CPU. Otherwise, the previous state of that pin may be read into the CPU, rather than the new state. When in doubt, it is better to separate these instructions with a NOP, or another instruction not accessing this I/O port. FIGURE 4-7: Q1 PC Instruction Instruction fetched Fetched Q2 SUCCESSIVE I/O OPERATION Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Note: This example shows write to PORTB followed by a read from PORTB. Note that: data setup time = (0.25 TCY - TPD) where TCY = instruction cycle and TPD = propagation delay of Q1 cycle to output valid. PC PC MOVWF PORTB Write to PORTB PC + 1 MOVF PORTB, W Read PORTB PC + 2 PC + 3 MOVWF PORTB MOVF PORTB, W NOP NOP NOP NOP RB<7:0> RB <7:0> Port pin sampled here TPD Therefore, at higher clock frequencies, a write followed by a read may be problematic. Execute Execute NOP NOP Execute Execute MOVWF MOVWF PORTB PORTB Execute Execute MOVF MOVF PORTB, W PORTB, W DS41140B-page 22 Preliminary 2002 Microchip Technology Inc. PIC16C432 5.0 LIN TRANSCEIVER 5.4 Thermal Shutdown The PIC16C432 has an integrated LIN transceiver which allows the microcontroller to communicate via LIN. The LIN protocol is handled by the microcontroller. The conversion from 5V signal to LIN signals is handled by the transceiver. In thermal shutdown, the LIN output is disabled instantaneously. The output transistor is turned off, regardless of the input level at pin LINTX bit and only a limited current can flow into the receiver connected to the LIN pin. 5.1 The LIN Protocol 5.5 The LIN protocol is not described within this document. For further information regarding the LIN protocol, please refer to www.lin-subbus.org. Wake-up From SLEEP Upon Bus Activity The PIC16C432 can wake-up from SLEEP upon bus activity in two ways: 1. 2. With the use of the comparators. Connecting BACT to one of PORTB<0,4:7> pins. 5.2 LIN Interfacing The LIN protocol is implemented and programmed by the user, using the LINTX and LINRX bits, which are used to interface to the transceiver. The LIN firmware transmits by toggling the LINTX bit in the LININTF register and is read by reading the LINRX bit in the PORTA register. All aspects of the protocol are handled by software (i.e., bit-banged), where the transceiver is used as the physical interface to the LIN network. For LIN software implementation, please refer to Microchip's website (www.microchip.com). Note: The LINTX is bit 2 of the LININTF register. If the LINTX bit is left cleared, no other nodes on the network will be able to communicate on the LIN for this is the dominate state for the protocol. The transceiver can be powered down by clearing the LINVDD bit in the LININTF register. This can be useful to reduce current consumption but does not allow the microcontroller to wake-up on LIN activity because the transceiver will be disabled. It is recommended that the firmware verify each bit transmitted, by comparing the LINTX and LINRX bits, to ensure no bus contention or hardware failure has occurred. The LINTX bit has no associated TRIS bit and is always an output. The LINRX bit has an associated TRIS bit, TLINRX, in the TRISA register. Note: TLINRX, bit 1 of TRISA register, must be set to '1' at all times. In case the comparators are used to wake-up the device upon bus activity, a reference to the LIN signal has to be supplied. This is usually VDD/2. The reference can either be an external reference or the internal voltage reference. Once the device is in SLEEP mode, the comparator interrupt will wake-up the device. On RESET, LINRX is configured as an analog comparator input (Section 8.1 of Data Sheet) which can be used to generate an interrupt to wake-up the device from SLEEP on bus activity. The LINRX bit will not receive data from the bus configured as an analog input, therefore, after wake-up from comparator interrupt or RESET, LINRX must be configured as a digital input to read the bus. The BACT output is a CMOS-levels representation of the LIN pin. This signal can be routed to one of the PORTB<0,4:7> pins. The RB0/INT external interrupt or PORTB<4:7> interrupt-on-change wakes up the device from SLEEP. Any one of the five PORTB pins can be used for wake-up where PORTB<0> offers multiple configuration options (Section 10.5.1 of Data Sheet) and PORTB<4:7> are interrupt-on-change (Section 10.5.3 of Data Sheet). Note: BACT pin is an output and must be left open if unused. 5.3 LIN Hardware Interface Figure 6-1 shows how to implement a hardware LIN interface in a master configuration and Figure 6-2 in a slave configuration using the PIC16C432. Figure 6-3 shows how to implement the hardware for a master configuration using BACT pin to generate a wake-up interrupt using RB0. The transceiver has an internal series resistor and diode, as defined in the LIN 1.2 specification, connecting VBAT and LIN. Note: No resistor is required between VBAT pin and 12V supply and for slave configuration, no resistor is required between VBAT and LIN. 2002 Microchip Technology Inc. Preliminary DS41140B-page 23 PIC16C432 FIGURE 5-1: TYPICAL LIN BUS MASTER APPLICATION +5V +12V VDD VBAT BACT PIC16C432 Note 2 1 k LIN Note 1 To LIN Bus VSS Note 1: Refer to LIN Bus Specification. 2: BACT pin should be left open if not used. FIGURE 5-2: TYPICAL LIN BUS SLAVE APPLICATION +5V +12V VDD VBAT BACT Note 2 PIC16C432 LIN To LIN Bus Note 1 VSS Note 1: May not be required. 2: BACT pin should be left open if not used. DS41140B-page 24 Preliminary 2002 Microchip Technology Inc. PIC16C432 FIGURE 5-3: LIN BUS APPLICATION USING WAKE-UP INTERRUPT +5V +12V VDD VBAT Note 1 BACT RB0 LIN 1k To LIN Bus Note 2 VSS PIC16C432 Note 1: May not be required. 2: For master configuration only. 2002 Microchip Technology Inc. Preliminary DS41140B-page 25 PIC16C432 REGISTER 5-1: LININTF REGISTER (ADDRESS: 90h) U-0 -- bit 7 bit 7-3 bit 2 Unimplemented: Read as '0' LINTX: LIN Bus Transmit bit 1 = LIN Bus line is high 0 = LIN Bus line is low Unimplemented: Read as '0' LINVDD: LIN Bus Transceiver VDD Supply bit 1 = VDD is supplied to the LIN Bus transceiver via microcontroller 0 = VDD is not supplied to the LIN Bus transceiver U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 LINTX U-0 -- R/W-1 LINVDD bit 0 bit 1 bit 0 Note 1: Transceiver VDD is same as microcontroller VDD. Legend: R = Readable bit -n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown TABLE 5-1: Address 05h 85h 90h Name PORTA TRISA LININTF SUMMARY OF REGISTERS ASSOCIATED WITH LIN TRANSCEIVER Bit 7 -- -- -- Bit 6 -- -- -- Bit 5 -- -- -- Bit 4 RA4 TRISA4 -- Bit 3 RA3 TRISA3 -- Bit 2 RA2 TRISA2 LINTX Bit 1 LINRX TLINRX(2) -- Bit 0 RA0 TRISA0 LINVDD Value on POR Value on All Other RESETS ---x 0000 ---u 0000 ---1 1111 ---1 1111 ---- -1-1 ---- -1-1 Legend: x = unknown, u = unchanged, -- = Unimplemented locations read as `0'. Note 1: Shaded bits are not used by LIN transceiver 2: TLINRX must be set to `1' at all times. DS41140B-page 26 Preliminary 2002 Microchip Technology Inc. PIC16C432 6.0 TIMER0 MODULE The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock bit (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2. The prescaler is shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. Section 6.3 details the operation of the prescaler. Figure 6-1 is a simplified block diagram of the Timer0 module. Timer mode is selected by clearing the T0CS bit (OPTION<5>). In Timer mode, the TMR0 will increment every instruction cycle (without prescaler). If Timer0 is written, the increment is inhibited for the following two cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to TMR0. Counter mode is selected by setting the T0CS bit. In this mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the source edge (T0SE) control 6.1 Timer0 Interrupt Timer0 interrupt is generated when the TMR0 register timer/counter overflows from FFh to 00h. This overflow sets the T0IF bit. The interrupt can be masked by clearing the T0IE bit (INTCON<5>). The T0IF bit (INTCON<2>) must be cleared in software by the Timer0 module Interrupt Service Routine, before reenabling this interrupt. The Timer0 interrupt cannot wake the processor from SLEEP, since the timer is shut-off during SLEEP. See Figure 6-4 for Timer0 interrupt timing. FIGURE 6-1: RA4/T0CKI pin TIMER0 BLOCK DIAGRAM Data Bus FOSC/4 0 1 1 Programmable Prescaler 0 PSOUT Sync with Internal clocks (2 TCY delay) Set Flag bit T0IF on Overflow TMR0 PSOUT 8 T0SE PS<2:0> T0CS PSA Note 1: Bits T0SE, T0CS, PS2, PS1, PS0 and PSA are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer (Figure 6-6). FIGURE 6-2: PC (Program Counter) Instruction Fetch TMR0 Instruction Executed T0 TIMER0 (TMR0) TIMING: INTERNAL CLOCK/NO PRESCALER Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC MOVWF TMR0 PC+1 MOVF TMR0,W PC+2 MOVF TMR0,W PC+3 MOVF TMR0,W PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6 T0+1 T0+2 NT0 NT0+1 NT0+2 T0 Write TMR0 executed Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 + 1 Read TMR0 reads NT0 + 2 2002 Microchip Technology Inc. Preliminary DS41140B-page 27 PIC16C432 FIGURE 6-3: PC (Program Counter) Instruction Fetch TMR0 Instruction Execute T0 TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC MOVWF TMR0 PC+1 MOVF TMR0,W PC+2 MOVF TMR0,W PC+3 MOVF TMR0,W PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6 T0+1 NT0 NT0+1 Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1 FIGURE 6-4: Q1 TIMER0 INTERRUPT TIMING Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(3) TMR0 Timer T0IF bit (INTCON<2>) GIE bit (INTCON<7>) Interrupt Latency Time FEh 1 FFh 1 00h 01h 02h INSTRUCTION FLOW PC Instruction Fetched Instruction Executed PC Inst (PC) Inst (PC-1) PC +1 Inst (PC+1) Dummy cycle PC +1 0004h Inst (0004h) Dummy cycle 0005h Inst (0005h) Inst (0004h) Inst (PC) Note 1: T0IF interrupt flag is sampled here (every Q1). 2: Interrupt latency = 3Tcy, where Tcy = instruction cycle time. 3: CLKOUT is available only in RC Oscillator mode. DS41140B-page 28 Preliminary 2002 Microchip Technology Inc. PIC16C432 6.2 Using Timer0 with External Clock When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type prescaler, so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns), divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. 6.2.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-5). Therefore, it is necessary for T0CKI to be high for at least 2TOSC (and a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device. 6.2.2 TIMER0 INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the TMR0 is actually incremented. Figure 6-5 shows the delay from the external clock edge to the timer incrementing. FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse misses sampling External Clock Input or Prescaler Output(2) (1) External Clock/Prescaler Output after Sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 (3) T0 + 2 Note 1: Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC (Duration of Q = TOSC). Therefore, the error in measuring the interval between two edges on Timer0 input = 4 TOSC max. 2: External clock if no prescaler selected, prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. 2002 Microchip Technology Inc. Preliminary DS41140B-page 29 PIC16C432 6.3 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 6-6). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that there is only one prescaler available, which is mutually exclusive between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer and vice-versa. The PSA and PS<2:0> bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (i.e., CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable. FIGURE 6-6: CLKOUT (= FOSC/4) BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER Data Bus 8 1 0 M U X SYNC 2 Cycles TMR0 reg 0 T0CKI pin 1 T0SE M U X T0CS PSA Set Flag bit T0IF on Overflow 0 M U X 8-bit Prescaler 8 8-to-1MUX PS<2:0> Watchdog Timer 1 PSA 0 MUX 1 PSA WDT Enable bit WDT Timeout Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. DS41140B-page 30 Preliminary 2002 Microchip Technology Inc. PIC16C432 6.3.1 SWITCHING PRESCALER ASSIGNMENT EXAMPLE 6-2: CHANGING PRESCALER (WDTTIMER0) ;Clear WDT and ;prescaler STATUS, RP0 b'xxxx0xxx' ;Select TMR0, new ;prescale value and ;clock source The prescaler assignment is fully under software control (i.e., it can be changed "on-the-fly" during program execution). To avoid an unintended device RESET, the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to WDT. CLRWDT BSF MOVLW EXAMPLE 6-1: 1.BCF CHANGING PRESCALER (TIMER0WDT) MOVWF BCF OPTION_REG STATUS, RP0 ;Skip if already in ; Bank 0 2.CLRWDT ;Clear WDT 3.CLRF TMR0 ;Clear TMR0 & Prescaler 4.BSF STATUS, RP0 ;Bank 1 5.MOVLW '00101111'b ;These 3 lines (5, 6, 7) 6.MOVWF OPTION ; are required only ; if desired PS<2:0> ; are 7.CLRWDT ; 000 or 001 8.MOVLW '00101xxx'b ;Set Postscaler to 9.MOVWF OPTION ; desired WDT rate 10.BCF STATUS, RP0 ;Return to Bank 0 STATUS, RP0 To change prescaler from the WDT to the TMR0 module, use the sequence shown in Example 6-2. This precaution must be taken, even if the WDT is disabled. TABLE 6-1: Address 01h 0Bh/8Bh 81h 85h REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR Value on All Other RESETS Name TMR0 INTCON OPTION TRISA Timer0 module register GIE RBPU -- PEIE INTEDG -- T0IE T0CS -- INTE T0SE TRISA4 RBIE PSA TRISA3 T0IF PS2 TRISA2 INTF PS1 TLINRX(2) RBIF PS0 TRISA0 xxxx xxxx uuuu uuuu 0000 000x 0000 000u 1111 1111 1111 1111 ---1 1111 ---1 1111 Legend: -- = Unimplemented locations, read as `0', x = unknown, u = unchanged Note 1: Shaded bits are not used by TMR0 module. 2: TLINRX must be set to `1' at all times. 2002 Microchip Technology Inc. Preliminary DS41140B-page 31 PIC16C432 NOTES: DS41140B-page 32 Preliminary 2002 Microchip Technology Inc. PIC16C432 7.0 COMPARATOR MODULE The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with the RA0 through RA3 pins. The onchip voltage reference (Section 8.0) can also be an input to the comparators. The CMCON register, shown in Register 7-1, controls the comparator input and output multiplexers. A block diagram of the comparator is shown in Figure 7-1. REGISTER 7-1: CMCON REGISTER (ADDRESS 1Fh) R-0 C2OUT bit7 R-0 C1OUT U-0 -- U-0 -- R/W-0 CIS R/W-0 CM2 R/W-0 CM1 R/W-0 CM0 bit0 bit 7 C2OUT: Comparator 2 Output bit 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINC1OUT: Comparator 1 Output bit 1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINUnimplemented: Read as '0' CIS: Comparator Input Switch bit When CM<2:0> = 001: 1 = C1 VIN- connects to RA3 0 = C1 VIN- connects to RA0 When CM<2:0> = 010: 1 = C1 VIN- connects to RA3 C2 VIN- connects to RA2 0 = C1 VIN- connects to RA0 C2 VIN- connects to LINRX bit 6 bit 5-4 bit 3 bit 2-0 CM<2:0>: Comparator Mode bits (See Figure 7-1) Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 7.1 Comparator Configuration There are eight modes of operation for the comparators. The CMCON register is used to select the mode. Figure 7-1 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode. If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Table 12-1. Note: Comparator interrupts should be disabled during a Comparator mode change, otherwise a false interrupt may occur. 2002 Microchip Technology Inc. Preliminary DS41140B-page 33 PIC16C432 FIGURE 7-1: A RA0/AN0 A RA3/AN3 A LINRX A RA2/AN2 VIN+ VIN- COMPARATOR I/O OPERATING MODES VIN- VIN+ C1 + C2 + Off (Read as `0') CM<2:0> = 000 Off (Read as `0') D RA0/AN0 D RA3/AN3 D LINRX D RA2/AN2 VIN+ VINVIN- VIN+ C1 + C2 + Off (Read as `0') CM<2:0> = 111 Comparators Off RA0/AN0 C1 + LINRX A C2 A VIN+ + CM<2:0> = 011 C2OUT RA2/AN2 A C1OUT A CIS=0 VINCIS=1 VIN+ C1 + C1OUT Off (Read as `0') Comparators Reset A RA0/AN0 A RA3/AN3 A LINRX RA2/AN2 VIN- VIN+ VIN- RA3/AN3 A CIS=0 VINCIS=1 VIN+ C2 + From VREF Module C2OUT Two Common Reference Comparators A RA0/AN0 D RA3/AN3 A LINRX A RA2/AN2 VIN+ VINVIN- VIN+ C1 + C2 + CM<2:0> = 011 Two Common Reference Comparators C2OUT C1OUT Four Inputs Multiplexed to Two Comparators A RA0/AN0 D RA3/AN3 A LINRX A RA2/AN2 RA4 VIN+ VINVIN- VIN+ C1 + CM<2:0> = 010 Off (Read as `0') C2 + Off (Read as `0') CM<2:0> = 110 Open Drain Two Common Reference Comparators with Outputs A D RA0/AN0 D RA3/AN3 A LINRX A RA2/AN2 VIN- VIN+ C1 + Off (Read as `0') RA0/AN0 A RA3/AN3 LINRX C2 C2OUT RA2/AN2 CM<2:0> = 101 A A CIS=0 VIN- CIS=1 VIN+ + VIN- - C1 C1OUT VIN- VIN+ + C2 VIN+ + C2OUT One Independent Comparators Legend: A = Analog Input, Port Reads `0' Always Three Inputs Multiplexed to Two Comparators CM<2:0> = 001 D = Digital Input CIS = CMCON<3>, Comparator Input Switch DS41140B-page 34 Preliminary 2002 Microchip Technology Inc. PIC16C432 The code example in Example 7-1 depicts the steps required to configure the comparator module. RA3 and RA4 are configured as digital output. RA0 and RA1 are configured as the V- inputs and RA2 as the V+ input to both comparators. EXAMPLE 7-1: FLAG_REG EQU CLRF FLAG_REG CLRF PORTA MOVF CMCON,W ANDLW 0xC0 IORWF FLAG_REG,F MOVLW 0x03 MOVWF CMCON BSF STATUS,RP0 MOVLW 0x07 MOVWF TRISA INITIALIZING COMPARATOR MODULE BCF CALL MOVF BCF BSF BSF BCF BSF BSF 0X20 ;Init flag register ;Init PORTA ;Move comparator contents to W ;Mask comparator bits ;Store bits in flag register ;Init comparator mode ;CM<2:0> = 011 ;Select Bank1 ;Initialize data direction ;Set RA<2:0> as inputs ;RA<4:3> as outputs ;TRISA<7:5> always read `0' STATUS,RP0 ;Select Bank 0 DELAY 10 ;10ms delay CMCON,F ;Read CMCON to end change condition PIR1,CMIF ;Clear pending interrupts STATUS,RP0 ;Select Bank 1 PIE1,CMIE ;Enable comparator interrupts STATUS,RP0 ;Select Bank 0 INTCON,PEIE ;Enable peripheral interrupts INTCON,GIE ;Global interrupt enable 7.2 Comparator Operation A single comparator is shown in Figure 7-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 7-2 represent the uncertainty due to input offsets and response time. 7.3 Comparator Reference An external or internal reference signal may be used, depending on the Comparator Operating mode. The analog signal that is present at VIN- is compared to the signal at VIN+, and the digital output of the comparator is adjusted accordingly (Figure 7-2). 2002 Microchip Technology Inc. Preliminary DS41140B-page 35 PIC16C432 FIGURE 7-2: VIN+ VIN+ SINGLE COMPARATOR Output - VINVIN+ Output 7.3.1 EXTERNAL REFERENCE SIGNAL When external voltage references are used, the comparator module can be configured to have the comparators operate from the same, or different reference sources. However, threshold detector applications may require the same reference. The reference signal must be between VSS and VDD and can be applied to either pin of the comparator(s). 7.3.2 INTERNAL REFERENCE SIGNAL The comparator module also allows the selection of an internally generated voltage reference for the comparators. Section 8.0, Voltage Reference Module, contains a detailed description of the Voltage Reference Module that provides this signal. The internal reference signal is used when the comparators are in mode CM<2:0> = 010 (Figure 7-1). In this mode, the internal voltage reference is applied to the VIN+ pin of both comparators. 7.4 Comparator Response Time Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs, otherwise the maximum delay of the comparators should be used (Table 12.1). DS41140B-page 36 Preliminary 2002 Microchip Technology Inc. PIC16C432 7.5 Comparator Outputs The comparator outputs are read through the CMCON register. These bits are read only. The comparator outputs may also be directly output to the RA3 and RA4 I/O pins. When the CM<2:0> = 110, multiplexors in the output path of the RA3 and RA4 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. Figure 73 shows the comparator output block diagram. The TRISA bits will still function as an output enable/ disable for the RA3 and RA4 pins while in this mode. Note 1: When reading the PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert an analog input according to the Schmitt Trigger input specification. 2: Analog levels on any pin that is defined as a digital input may cause the input buffer to consume more current than is specified. 2002 Microchip Technology Inc. Preliminary DS41140B-page 37 PIC16C432 FIGURE 7-3: COMPARATOR OUTPUT BLOCK DIAGRAM Port Pins MULTIPLEX + To RA3 or RA4 Pin Data Bus RD CMCON Q D EN - Set CMIF bit Q From Other Comparator D EN CL RD CMCON NRESET DS41140B-page 38 Preliminary 2002 Microchip Technology Inc. PIC16C432 7.6 Comparator Interrupts 7.9 The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that has occurred. The CMIF bit, PIR1<6>, is the comparator interrupt flag. The CMIF bit must be reset by clearing `0'. Since it is also possible to write a '1' to this register, a simulated interrupt may be initiated. The CMIE bit (PIE1<6>) and the PEIE bit (INTCON<6>) must be set to enable the interrupt. In addition, the GIE bit must also be set. If any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs. Note: If a change in the CMCON register (C1OUT or C2OUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF (PIR1<6>) interrupt flag may not get set. Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 7-4. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latchup may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of CMCON. This will end the mismatch condition. Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared. 7.7 Comparator Operation During SLEEP When a comparator is active and the device is placed in SLEEP mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will wake-up the device from SLEEP mode when enabled. While the comparator is powered up, higher SLEEP currents than shown in the power-down current specification will occur. Each comparator that is operational will consume additional current as shown in the comparator specifications. To minimize power consumption while in SLEEP mode, turn off the comparators, CM<2:0> = 111, before entering SLEEP. If the device wakes up from SLEEP, the contents of the CMCON register are not affected. 7.8 Effects of a RESET A device RESET forces the CMCON register to its RESET state. This forces the comparator module to be in the Comparator RESET mode, CM<2:0> = 000. This ensures that all potential inputs are analog inputs. Device current is minimized when analog inputs are present at RESET time. The comparators will be powered down during the RESET interval. 2002 Microchip Technology Inc. Preliminary DS41140B-page 39 PIC16C432 FIGURE 7-4: ANALOG INPUT MODEL VDD VT = 0.6V RS < 10 K AIN VA CPIN 5 pF RIC VT = 0.6V ILEAKAGE 500 nA VSS Legend CPIN VT ILEAKAGE RIC RS VA = Input capacitance = Threshold voltage = Leakage current at the pin due to various junctions = Interconnect resistance = Source impedance = Analog voltage TABLE 7-1: Address 1Fh 9Fh 0Bh 0Ch 8Ch 85h Name REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 C2OUT VREN GIE -- -- -- Bit 6 C1OUT VROE PEIE CMIF CMIE -- Bit 5 -- VRR T0IE -- -- -- Bit 4 -- -- INTE -- -- TRISA4 Bit 3 CIS VR3 RBIE -- -- TRISA3 Bit 2 CM2 VR2 T0IF -- -- Bit 1 CM1 VR1 INTF -- -- (1) Bit 0 CM0 VR0 RBIF -- -- TRISA0 Value on: POR Value on All Other RESETS CMCON VRCON INTCON PIR1 PIE1 TRISA 00-- 0000 00-- 0000 000- 0000 000- 0000 0000 000x 0000 000u -0-- ---- -0-- ----0-- ---- -0-- ------1 1111 ---1 1111 TRISA2 TLINRX Legend: -- = Unimplemented, read as `0', x = unknown, u = unchanged Note 1: TLINRX must be set to `1' at all times. DS41140B-page 40 Preliminary 2002 Microchip Technology Inc. PIC16C432 8.0 VOLTAGE REFERENCE MODULE 8.1 Configuring the Voltage Reference The Voltage Reference can output 16 distinct voltage levels for each range. The equations used to calculate the output of the Voltage Reference are as follows: if VRR = 1: VREF = (VR<3:0>/24) x VDD if VRR = 0: VREF = (VDD x 1/4) + (VR<3:0>/32) x VDD The setting time of the Voltage Reference must be considered when changing the VREF output (Table 12.1). Example 8-1 shows an example of how to configure the Voltage Reference for an output voltage of 1.25V with VDD = 5.0V. The Voltage Reference is a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of VREF values and has a power-down function to conserve power when the reference is not being used. The VRCON register controls the operation of the reference as shown in Register 8-1. The block diagram is given in Figure 8-1. REGISTER 8-1: VRCON REGISTER (ADDRESS 9Fh) R/W-0 VREN bit7 R/W-0 VROE R/W-0 VRR U-0 -- R/W-0 VR3 R/W-0 VR2 R/W-0 VR1 R/W-0 VR0 bit0 bit 7 VREN: VREF Enable bit 1 = VREF circuit powered on 0 = VREF circuit powered down, no IDD drain VROE: VREF Output Enable bit 1 = VREF is output on RA2 pin 0 = VREF is disconnected from RA2 pin VRR: VREF Range Selection bit 1 = Low Range 0 = High Range Unimplemented: Read as '0' VR<3:0>: VREF Value Selection 0 VR [3:0] 15 when VRR = 1: VREF = (VR<3:0>/ 24) * VDD when VRR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3-0 FIGURE 8-1: VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages VREN 8R R R R R 8R VRR VR3 VREF 16-1 Analog Mux VR0 (From VRCON<3:0>) Note 1: R is defined in Table 12-2. 2002 Microchip Technology Inc. Preliminary DS41140B-page 41 PIC16C432 EXAMPLE 8-1: MOVLW MOVWF BSF MOVLW MOVWF MOVLW MOVWF BCF CALL 0x02 CMCON STATUS,RP0 0x07 TRISA 0xA6 VRCON STATUS,RP0 DELAY10 VOLTAGE REFERENCE CONFIGURATION ; 4 Inputs Muxed ; to 2 comps. ; go to Bank 1 ; RA3-RA0 are ; outputs ; enable VREF ; low range ; set VR<3:0>=6 ; go to Bank 0 ; 10s delay 8.4 Effects of a RESET A device RESET disables the Voltage Reference by clearing bit VREN (VRCON<7>). This RESET also disconnects the reference from the RA2 pin by clearing bit VROE (VRCON<6>) and selects the high voltage range by clearing bit VRR (VRCON<5>). The VREF value select bits, VRCON<3:0>, are also cleared. 8.5 Connection Considerations 8.2 Voltage Reference Accuracy/Error The full range of VSS to VDD cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 81) keep VREF from approaching VSS or VDD. The Voltage Reference is VDD derived and therefore, the VREF output changes with fluctuations in VDD. The absolute accuracy of the Voltage Reference can be found in Table 12-2. The Voltage Reference Module operates independently of the comparator module. The output of the reference generator may be connected to the RA2 pin if the TRISA<2> bit is set and the VROE bit, VRCON<6>, is set. Enabling the Voltage Reference output onto the RA2 pin, with an input signal present, will increase current consumption. Connecting RA2 as a digital output with VREF enabled will also increase current consumption. The RA2 pin can be used as a simple D/A output with limited drive capability. Due to the limited drive capability, a buffer must be used in conjunction with the Voltage Reference output for external connections to VREF. Figure 8-2 shows an example buffering technique. 8.3 Operation During SLEEP When the device wakes up from SLEEP through an interrupt or a Watchdog Timer timeout, the contents of the VRCON register are not affected. To minimize current consumption in SLEEP mode, the Voltage Reference should be disabled. FIGURE 8-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE VREF Module R(1) RA2 * Voltage Reference Output Impedance + - * VREF Output Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>. TABLE 8-2: Address 9Fh 1Fh 85h Name REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE Bit 7 VREN C2OUT -- Bit 6 VROE C1OUT -- Bit 5 VRR -- -- Bit 4 -- -- TRISA4 Bit 3 VR3 CIS TRISA3 Bit 2 VR2 CM2 Bit 1 VR1 CM1 Bit 0 VR0 CM0 Value On POR/BOD 000- 0000 00-- 0000 ---1 1111 Value On All Other RESETS 000- 0000 00-- 0000 ---1 1111 VRCON CMCON TRISA TRISA2 TLINRX(1) TRISA0 Legend: -- = Unimplemented, read as `0' Note 1: TLINRX must be set to `1' at all times. DS41140B-page 42 Preliminary 2002 Microchip Technology Inc. PIC16C432 9.0 SPECIAL FEATURES OF THE CPU The PIC16C432 has a Watchdog Timer which is controlled by configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only, and is designed to keep the part in RESET while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which provides at least a 72 ms RESET. With these three functions on-chip, most applications need no external RESET circuitry. The SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost, while the LP crystal option saves power. A set of configuration bits are used to select various options. Special circuits to deal with the needs of real-time applications are what sets a microcontroller apart from other processors. The PIC16C432 device has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: 1. 2. OSC Selection RESET Power-on Reset (POR) Power-up Timer (PWRT) Oscillator Start-Up Timer (OST) Brown-out Reset (BOD) Interrupts Watchdog Timer (WDT) SLEEP Code Protection ID Locations In-circuit Serial Programming 3. 4. 5. 6. 7. 8. 9.1 Configuration Bits The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. These bits are mapped in program memory location 2007h. The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/configuration memory space (2000h - 3FFFh), which can be accessed only during programming. 2002 Microchip Technology Inc. Preliminary DS41140B-page 43 PIC16C432 REGISTER 9-1: CP1 CONFIGURATION WORD CP0(2) CP1 CP0(2) CP1 CP0(2) -- BODEN(1) CP1 CP0(2) PWRTE(1) WDTE F0SC1 F0SC0 bit 13 bit 13-8 bit 5-4 CP1:CP0 Pairs: Code protection bit pairs(2) Code protection for 2K program memory bits 11 = Program memory code protection off 10 = 0400h-07FFh code protected 01 = 0200h-07FFh code protected 00 = 0000h-07FFh code protected Unimplemented: Read as '1' BODEN: Brown-out Reset Enable bit (1) 1 = BOD enabled 0 = BOD disabled PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator bit 0 bit 7 bit 6 bit 3 bit 2 bit 1-0 Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset in enabled. 2: All of the CP<1:0> pairs have to be given the same value to enable the code protection scheme listed. Legend: R = Readable bit -n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown DS41140B-page 44 Preliminary 2002 Microchip Technology Inc. PIC16C432 9.2 9.2.1 Oscillator Configurations OSCILLATOR TYPES TABLE 9-1: CERAMIC RESONATORS, PIC16C432 Ranges Tested: Freq OSC1 OSC2 The PIC16C432 can be operated in four different oscillator options. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: * * * * LP - Low Power Crystal XT - Crystal/Resonator HS - High Speed Crystal/Resonator RC - Resistor/Capacitor Mode XT 455 kHz 68 - 100 pF 68 - 100 pF 2.0 MHz 15 - 68 pF 15 - 68 pF 4.0 MHz 15 - 68 pF 15 - 68 pF HS 8.0 MHz 10 - 68 pF 10 - 68 pF 16.0 MHz 10 - 22 pF 10 - 22 pF These values are for design guidance only. See notes at bottom of page. 9.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS TABLE 9-2: In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation (Figure 9-1). The PIC16C432 oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1 pin (Figure 9-2). CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR, PIC16C432 Crystal Freq 32 kHz 200 kHz 200 kHz 1 MHz 4 MHz Cap. Range C1 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF Cap. Range C2 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF Osc Type LP XT FIGURE 9-1: CRYSTAL OPERATION (OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION) OSC1 HS 4 MHz 8 MHz 20 MHz These values are for design guidance only. See notes at bottom of page. C1 XTAL OSC2 C2 RS Note 2 RF To Internal Logic SLEEP Note 1: Recommended values of C1 and C2 are indentical to the ranges tested table. 2: Higher capacitance increases the stability of oscillator, but also increases the startup time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Rs may be required in HS mode, as well as XT mode, to avoid over driving crystals with low drive level specification. PIC16C432 Note 1: See Table 9-1 and Table 9-2 for recommended values of C1 and C2. 2: A series resistor may be required for AT strip cut crystals. FIGURE 9-2: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) Clock from ext. system Open OSC1 PIC16C432 OSC2 2002 Microchip Technology Inc. Preliminary DS41140B-page 45 PIC16C432 9.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT 9.2.4 RC OSCILLATOR For timing insensitive applications, the "RC" device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 9-5 shows how the R/C combination is connected to the PIC16C432. For REXT values below 2.2 k, the oscillator operation may become unstable, or stop completely. For very high REXT values (i.e., 1 M), the oscillator becomes sensitive to noise, humidity and leakage. Thus, it is recommended to keep REXT between 3 k and 100 k. Although the oscillator will operate with no external capacitor (CEXT = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance, or package lead frame capacitance. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more). See Section 2.0 for variation of oscillator frequency due to VDD for given REXT/CEXT values, as well as frequency variation due to operating temperature for given R, C, and VDD values. The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin and can be used for test purposes, or to synchronize other logic (see Figure 4-2 for waveform). Either a prepackaged oscillator can be used, or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with series resonance, or one with parallel resonance. Figure 9-3 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180 phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometers bias the 74AS04 in the linear region. This could be used for external oscillator designs. FIGURE 9-3: EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT To Other Devices +5V 10k 4.7k 74AS04 74AS04 PIC16C432 CLKIN 10k XTAL 10k 20 pF 20 pF Figure 9-4 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180 phase shift in a series resonant oscillator circuit. The 330 k resistors provide the negative feedback to bias the inverters in their linear region. FIGURE 9-5: VDD RC OSCILLATOR MODE FIGURE 9-4: EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT To other Devices 74AS04 PIC16C432 CLKIN PIC16C432 REXT OSC1 Internal Clock CEXT VDD FOSC/4 OSC2/CLKOUT 330 74AS04 0.1 mF 330 74AS04 XTAL DS41140B-page 46 Preliminary 2002 Microchip Technology Inc. PIC16C432 9.3 RESET The PIC16C432 differentiates between various kinds of RESET: a) b) c) d) e) f) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset (normal operation) WDT wake-up (SLEEP) Brown-out Reset (BOD) WDT Reset and MCLR Reset during SLEEP. They are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different RESET situations, as indicated in Table 9-4. These bits are used in software to determine the nature of the RESET. See Table 9-6 for a full description of RESET states of all registers. A simplified block diagram of the On-chip Reset Circuit is shown in Figure 9-6. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Table 12-6 for pulse width specification. Some registers are not affected in any RESET condition. Their status is unknown on POR and unchanged in any other RESET. Most other registers are RESET to a "RESET state" on Power-on Reset, MCLR Reset, FIGURE 9-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR/ VPP pin WDT Module VDD Rise Detect VDD Brown-out Reset OST/PWRT WDT SLEEP Timeout Reset Power-on Reset S BODEN OST 10-bit Ripple-counter OSC1/ CLKIN pin On-chip(1) RC OSC PWRT 10-bit Ripple-counter Chip_Reset R Q Enable PWRT Enable OST See Table 9-3 for timeout situations. Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. 2002 Microchip Technology Inc. Preliminary DS41140B-page 47 PIC16C432 9.4 Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST) and Brown-out Reset (BOD) POWER-ON RESET (POR) The Power-Up time delay will vary from chip-to-chip and due to VDD, temperature and process variation. See DC parameters for details. 9.4.3 9.4.1 OSCILLATOR START-UP TIMER (OST) The on-chip POR circuit holds the chip in RESET until VDD has reached a high enough level for proper operation. To take advantage of the POR, just tie the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See electrical specifications for details. The POR circuit does not produce an internal RESET when VDD declines. When the device starts normal operation (exits the RESET condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting". The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST timeout is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP. 9.4.4 BROWN-OUT RESET (BOD) The PIC16C432 has an on-chip Brown-out Reset circuitry. A configuration bit, BOREN, can disable (if clear/ programmed), or enable (if set) the Brown-out Reset circuitry. If VDD falls below 4.0V (refer to BVDD parameter D005) for greater than parameter (TBOR) in Table 12-6, the brown-out situation will reset the chip. A RESET won't occur if VDD falls below 4.0V for less than parameter (TBOR). On any RESET (Power-on, Brown-out, Watchdog, etc.), the chip will remain in RESET until VDD rises above BVDD. The Power-up Timer will then be invoked and will keep the chip in RESET an additional 72 ms. If VDD drops below BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once VDD rises above BVDD, the Power-up Timer will execute a 72 ms RESET. The Power-up Timer should always be enabled when Brown-out Reset is enabled. Figure 9-7 shows typical Brown-out situations. 9.4.2 POWER-UP TIMER (PWRT) The Power-up Timer provides a fixed 72 ms (nominal) timeout on power-up only, from POR or Brown-out Reset. The Power-up Timer operates on an internal RC oscillator. The chip is kept in RESET as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A configuration bit, PWRTE, can disable (if set), or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should always be enabled when Brown-out Reset is enabled. FIGURE 9-7: VDD BROWN-OUT SITUATIONS BVDD Internal Reset VDD 72 ms BVDD Internal Reset <72 ms 72 ms VDD BVDD Internal Reset 72 ms DS41140B-page 48 Preliminary 2002 Microchip Technology Inc. PIC16C432 9.4.5 TIMEOUT SEQUENCE 9.4.6 On power-up, the timeout sequence is as follows: First PWRT timeout is invoked after POR has expired, then OST is activated. The total timeout will vary based on oscillator configuration and PWRTE bit status. For example, in RC mode with PWRTE bit erased (PWRT disabled), there will be no timeout at all. Figure 9-8, Figure 9-8 and Figure 9-9 depict timeout sequences. Since the timeouts occur from the POR pulse, if MCLR is kept low long enough, the timeouts will expire. Then bringing MCLR high will begin execution immediately (see Figure 9-8). This is useful for testing purposes or to synchronize more than one PICmicro(R) device operating in parallel. Table 9-5 shows the RESET conditions for some special registers, while Table 9-6 shows the RESET conditions for all the registers. POWER CONTROL (PCON)/STATUS REGISTER The power control/status register, PCON (address 8Eh), has two bits. Bit0 is BOR (Brown-out). BOR is unknown on Poweron Reset. It must then be set by the user and checked on subsequent RESETS to see if BOR = 0, indicating that a brown-out has occurred. The BOR status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (by setting BODEN bit = 0 in the Configuration word). Bit1 is POR (Power-on Reset). It is a `0' on Power-on Reset and unaffected otherwise. The user must write a `1' to this bit following a Power-on Reset. On a subsequent RESET, if POR is `0', it will indicate that a Poweron Reset must have occurred (VDD may have gone too low). TABLE 9-3: TIMEOUT IN VARIOUS SITUATIONS Power-up Brown-out Reset PWRTE = 0 PWRTE = 1 1024 TOSC -- 72 ms + 1024 TOSC 72 ms 72 ms + 1024 TOSC 72 ms Wake-up from SLEEP 1024 TOSC -- Oscillator Configuration XT, HS, LP RC TABLE 9-4: POR 0 0 0 1 1 1 1 1 STATUS/PCON BITS AND THEIR SIGNIFICANCE BOR X X X 0 1 1 1 1 TO 1 0 X X 0 0 u 1 PD 1 X 0 X u 0 u 0 Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP Legend: x = unknown, u = unchanged 2002 Microchip Technology Inc. Preliminary DS41140B-page 49 PIC16C432 TABLE 9-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset WDT Wake-up Brown-out Reset Interrupt Wake-up from SLEEP Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1 (1) STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 uuuu uuu0 0uuu 000x xuuu uuu1 0uuu PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --u0 ---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and global enable bit GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC+1. TABLE 9-6: INITIALIZATION CONDITION FOR REGISTERS MCLR Reset during Normal Operation MCLR Reset during SLEEP WDT Reset Brown-out Reset(1) uuuu uuuu uuuu uuuu 0000 0000 000q quuu(4) uuuu uuuu ---u uuuu uuuu uuuu 00-- 0000 ---0 0000 0000 000u -0-- ---1111 1111 ---1 1111 1111 1111 -0-- ------- --uq(1,6) ---- -1-1 000- 0000 Wake-up from SLEEP through Interrupt Wake-up from SLEEP through WDT Timeout uuuu uuuu uuuu uuuu PC + 1(3) uuuq quuu(4) uuuu uuuu ---u uuuu uuuu uuuu uu-- uuuu ---u uuuu uuuu uqqq(2) -q-- ----(2,5) uuuu uuuu ---u uuuu uuuu uuuu -u-- ------- --uu ---- -1-1 uuu- uuuu Register Address Power-on Reset W INDF TMR0 PCL STATUS FSR PORTA PORTB CMCON PCLATH INTCON PIR1 OPTION TRISA TRISB PIE1 PCON LININTF VRCON Legend: Note 1: 2: 3: -- 00h 01h 02h 03h 04h 05h 06h 1Fh 0Ah 0Bh 0Ch 81h 85h 86h 8Ch 8Eh 90h 9Fh xxxx xxxx -- xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx ---x xxxx xxxx xxxx 00-- 0000 ---0 0000 0000 000x -0-- ---1111 1111 ---1 1111 1111 1111 -0-- ------- --0x ---- -111 000- 0000 u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 4: See Table 9-5 for RESET value for specific conditions. 5: If wake-up was due to comparator input changing , then bit 6 = 1. All other interrupts generating a wakeup will cause bit 6 = u. 6: If RESET was due to brown-out, then PCON bit0 = 0. All other RESETS will cause bit0 = u. DS41140B-page 50 Preliminary 2002 Microchip Technology Inc. PIC16C432 FIGURE 9-8: TIMEOUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIMEOUT TOST OST TIMEOUT INTERNAL RESET FIGURE 9-9: TIMEOUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIMEOUT TOST OST TIMEOUT INTERNAL RESET FIGURE 9-10: VDD MCLR INTERNAL POR TIMEOUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) TPWRT PWRT TIMEOUT TOST OST TIMEOUT INTERNAL RESET 2002 Microchip Technology Inc. Preliminary DS41140B-page 51 PIC16C432 FIGURE 9-11: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) FIGURE 9-13: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2 VDD R1 D R R1 MCLR C R2 Q1 MCLR 40k VDD VDD VDD PIC16C432 PIC16C432 Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: < 40 k is recommended to make sure that voltage drop across R does not violate the device's electrical specification. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C, in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD), or Electrical Overstress (EOS). Note 1: This brown-out circuit is less expensive, albeit less accurate. Transistor Q1 turns off when VDD is below a certain level such that: R1 VDD x R1 + R2 = 0.7V 2: Internal brown-out detection should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor. FIGURE 9-14: VDD MCP809 EXTERNAL BROWN-OUT PROTECTION CIRCUIT 3 FIGURE 9-12: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1 VDD VSS RST VDD 33k 10k 40k VDD Bypass Capacitor VDD MCLR MCLR PIC16C432 This brown-out protection circuit employs Microchip Technology's MCP809 microcontroller supervisor. The MCP8XX and MCP1XX families of supervisors provide push-pull and open collector outputs with both high and low active RESET pins. There are 7 different trip point selections to accommodate 5V and 3V systems. PIC16C432 Note 1: This circuit will activate RESET when VDD goes below (Vz + 0.7V), where Vz = Zener voltage. 2: Internal Brown-out Reset circuitry should be disabled when using this circuit. DS41140B-page 52 Preliminary 2002 Microchip Technology Inc. PIC16C432 9.5 * * * * * Interrupts The PIC16C432 has 4 sources of interrupt: External interrupt RB0/INT TMR0 overflow interrupt PORTB change interrupts (pins RB<7:4>) Comparator interrupt LIN Bus wake-up can be wired to RB0, or comparator When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid RB0/INT recursive interrupts. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends on when the interrupt event occurs (Figure 916). The latency is the same for one or two cycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Note 1: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. 2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The CPU will execute a NOP in the cycle immediately following the instruction which clears the GIE bit. The interrupts which were ignored are still pending to be serviced when the GIE bit is set again. The interrupt control register (INTCON) and the Peripheral Interrupt Register (PIR1) record individual interrupt requests in flag bits. INTCON and PIR1 have individual and global interrupt enable bits. A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts, or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in INTCON register. GIE is cleared on RESET. The "return from interrupt" instruction, RETFIE, exits interrupt routine, as well as sets the GIE bit, which reenables all unmasked interrupts. The INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flag is contained in the special register PIR1. The corresponding interrupt enable bit is contained in special registers PIE1. FIGURE 9-15: INTERRUPT LOGIC T0IF T0IE INTF INTE RBIF RBIE Interrupt to CPU Wake-up (If in SLEEP mode) CMIF CMIE PEIE GIE 2002 Microchip Technology Inc. Preliminary DS41140B-page 53 PIC16C432 9.5.1 RB0/INT INTERRUPT 9.5.2 TMR0 INTERRUPT External interrupt on RB0/INT pin is edge triggered; either rising if INTEDG bit (OPTION<6>) is set, or falling, if INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in software in the Interrupt Service Routine before reenabling this interrupt. The RB0/INT interrupt can wake-up the processor from SLEEP, if the INTE bit was set prior to going into SLEEP. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up. See Section 9.8 for details on SLEEP and Figure 9-18 for timing of wakeup from SLEEP through RB0/INT interrupt. An overflow (FFh 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. For operation of the Timer0 module, see Section 6.0. 9.5.3 PORTB INTERRUPT An input change on PORTB <7:4> sets the RBIF (INTCON<0>) bit. The interrupt can be enabled/disabled by setting/clearing the RBIE (INTCON<4>) bit. For operation of PORTB (Section 4.2). Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set. 9.5.4 COMPARATOR INTERRUPT See Section 7.6 for complete description of comparator interrupts. FIGURE 9-16: INT PIN INTERRUPT TIMING Q1 OSC1 CLKOUT 3 INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 4 1 5 Interrupt Latency 2 1 PC Inst (PC) Inst (PC-1) PC+1 Inst (PC+1) Inst (PC) PC+1 -- Dummy Cycle 0004h Inst (0004h) Dummy Cycle 0005h Inst (0005h) Inst (0004h) Note 1: INTF flag is sampled here (every Q1). 2: Interrupt latency = 1-4 Tcy where Tcy = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC Oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. DS41140B-page 54 Preliminary 2002 Microchip Technology Inc. PIC16C432 9.6 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (i.e., W register and STATUS register). This will have to be implemented in software. Example 9-7 stores and restores the STATUS and W registers. The user register, W_TEMP, must be defined in both banks and must be defined at the same offset from the bank base address (i.e., W_TEMP is defined at 0x70 in Bank 0 and it must also be defined at 0xF0 in Bank 1). The user register, STATUS_TEMP, must be defined in Bank 0. The Example 9-7: * * * * Stores the W register Stores the STATUS register in Bank 0 Executes the ISR code Restores the STATUS (and bank select bit register) * Restores the W register EXAMPLE 9-7: SAVING THE STATUS AND W REGISTERS IN RAM ;copy W to temp register, ;could be in either bank ;swap status to be saved into W ;change to bank 0 regardless ;of current bank MOVW F SWAP F BCF W_TEMP STATUS,W STATUS,RP0 MOVW F : : : SWAP F STATUS_TEMP ;save status to bank 0 ;register (ISR) STATUS_TEMP ;swap STATUS_TEMP regis,W ter ;into W, sets bank to original ;state STATUS W_TEMP,F W_TEMP,W ;move W into STATUS register ;swap W_TEMP ;swap W_TEMP into W MOVW F SWAP F SWAP F 2002 Microchip Technology Inc. Preliminary DS41140B-page 55 PIC16C432 9.7 Watchdog Timer (WDT) The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the CLKIN pin. That means that the WDT will run even if the clock on the OSC1 and OSC2 pins of the device have been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT timeout generates a device RESET. If the device is in SLEEP mode, a WDT timeout causes the device to wake-up and continue with normal operation. The WDT can be permanently disabled by programming the configuration bit WDTE as clear (Section 9.1). DC specs). If longer timeout periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control, by writing to the OPTION register. Thus, timeout periods up to 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET. The TO bit in the STATUS register will be cleared upon a Watchdog Timer timeout. 9.7.2 WDT PROGRAMMING CONSIDERATIONS 9.7.1 WDT PERIOD The WDT has a nominal timeout period of 18 ms, (with no prescaler). The timeout periods vary with temperature, VDD and process variations from part to part (see It should also be taken in account that under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler), it may take several seconds before a WDT timeout occurs. FIGURE 9-17: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure 6-6) 0 Watchdog Timer * 1 M U X Postscaler 8 8 - to -1 MUX PS<2:0> WDT Enable Bit PSA * 0 MUX 1 To TMR0 (Figure 6-6) PSA WDT Timeout Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. TABLE 9-8: Address 2007h 81h _ SUMMARY OF WATCHDOG TIMER REGISTERS Name Config. bits OPTION Bit 7 -- RBPU Bit 6 BOREN INTEDG Bit 5 CP1 T0CS Bit 4 CP0 T0SE Bit 3 PWRTE PSA Bit 2 WDTE PS2 Bit 1 FOSC1 PS1 Bit 0 FOSC0 PS0 Legend: = Unimplemented location, read as "0", + = Reserved for future use Note 1: Shaded cells are not used by the Watchdog Timer. DS41140B-page 56 Preliminary 2002 Microchip Technology Inc. PIC16C432 9.8 Power-down Mode (SLEEP) 9.8.1 WAKE-UP FROM SLEEP The Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit in the STATUS register is cleared, the TO bit is set and the oscillator driver is turned off. The I/O ports maintain the status they had before SLEEP was executed (driving high, low, or hiimpedance). For lowest current consumption in this mode, all I/O pins should be either at VDD or VSS, with no external circuitry drawing current from the I/O pin, and the comparators and VREF should be disabled. I/O pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). Note: It should be noted that a RESET generated by a WDT timeout does not drive MCLR pin low. The device can wake-up from SLEEP through one of the following events: 1. 2. 3. 4. External RESET input on MCLR pin. Watchdog Timer Wake-up (if WDT was enabled). Interrupt from RB0/INT pin, RB Port change, or the Peripheral Interrupt (Comparator). LIN activity. The first event will cause a device RESET. The two latter events are considered a continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of device RESET. PD bit, which is set on power-up is cleared when SLEEP is invoked. TO bit is cleared if WDT wake-up occurred. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have an NOP after the SLEEP instruction. Note: If the global interrupts are disabled (GIE is cleared), but any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wake-up from SLEEP. The SLEEP instruction is completely executed. The WDT is cleared when the device wakes up from SLEEP, regardless of the source of wake-up. 2002 Microchip Technology Inc. Preliminary DS41140B-page 57 PIC16C432 FIGURE 9-18: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: PC Inst(PC) = SLEEP Inst(PC - 1) PC+1 Inst(PC + 1) SLEEP PC+2 PC+2 Inst(PC + 2) Inst(PC + 1) Dummy cycle PC + 2 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Processor in SLEEP Interrupt Latency TOST(2) XT, HS or LP Oscillator mode assumed. TOST = 1024TOSC (drawing not to scale). This delay does not occur for RC Osc mode. GIE = '1' assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in these osc modes, but shown here for timing reference. 9.9 Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: Microchip does not recommend code protecting windowed devices. 9.10 ID Locations After RESET, to place the device into Programming/ Verify mode, the program counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC16C6X/7X/9XX Programming Specifications (Literature #DS30228). A typical in-circuit serial programming connection is shown in Figure 9-19. Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during program/verify. Only the Least Significant 4 bits of the ID locations are used. FIGURE 9-19: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION To Normal Connections 9.11 In-Circuit Serial Programming External Connector Signals +5V 0V VPP CLK Data I/O The PIC16C432 microcontroller can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a Program/Verify mode by holding the RB6 and RB7 pins low, while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). RB6 becomes the programming clock and RB7 becomes the programming data. Both RB6 and RB7 are Schmitt Trigger inputs in this mode. PIC16C432 VDD VSS MCLR/VPP RB6 RB7 VDD To Normal Connections DS41140B-page 58 Preliminary 2002 Microchip Technology Inc. PIC16C432 10.0 INSTRUCTION SET SUMMARY The instruction set is highly orthogonal and is grouped into three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Table 10-1 lists the instructions recognized by the MPASM assembler. Figure 10-1 shows the three general formats that the instructions can have. Note: To maintain upward compatibility with future PICmicro(R) products, do not use the OPTION and TRIS instructions. Each PIC16C432 instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16C432 instruction set summary in Table 10-2 lists byte-oriented, bitoriented, and literal and control operations. Table 10-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. For literal and control operations, 'k' represents an eight- or eleven-bit constant, or literal value. TABLE 10-1: Field f W b k x OPCODE FIELD DESCRIPTIONS Description All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 Label name Top-of-Stack Program Counter Program Counter High Latch Global Interrupt Enable bit Watchdog Timer/Counter Timeout bit Power-down bit Destination, either the W register or the specified register file location Options Contents Assigned to Register bit field In the set of d label TOS PC PCLATH GIE WDT TO PD dest [ ( ] ) <> italics User defined term (font is courier) 2002 Microchip Technology Inc. Preliminary DS41140B-page 59 PIC16C432 FIGURE 10-1: GENERAL FORMAT FOR INSTRUCTIONS 0 Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 0 8 7 k (literal) 0 13 11 OPCODE 10 k (literal) 0 k = 11-bit immediate value DS41140B-page 60 Preliminary 2002 Microchip Technology Inc. PIC16C432 TABLE 10-2: Mnemonic, Operands PIC16C432 INSTRUCTION SET 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C,DC,Z Z Z Z Z Z Z Z Z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 C C C,DC,Z Z 1,2 1,2 1,2 1,2 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1(2) 1(2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z TO,PD Z TO,PD C,DC,Z Z Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTB, 1) the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second is executed as a NOP. 2002 Microchip Technology Inc. Preliminary DS41140B-page 61 PIC16C432 10.1 Instruction Descriptions Add Literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z 11 111x kkkk kkkk k ANDLW Syntax: Operands: Operation: Status Affected: Encoding: Description: AND Literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z 11 1001 kkkk kkkk k ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description: The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register. 1 1 ADDLW 0x15 The contents of W register are AND'ed with the eight bit literal 'k'. The result is placed in the W register. 1 1 ANDLW 0x5F Words: Cycles: Example Words: Cycles: Example Before Instruction W= 0x10 After Instruction W= 0x25 Before Instruction W= 0xA3 After Instruction W= 0x03 ADDWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (dest) C, DC, Z 00 0111 dfff ffff f,d ANDWF Syntax: Operands: Operation: Status Affected: Encoding: Description: AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (dest) Z 00 0101 dfff ffff f,d Add the contents of the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. 1 1 ADDWF FSR, 0 AND the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. 1 1 ANDWF FSR, 1 Words: Cycles: Example Words: Cycles: Example Before Instruction W = 0x17 FSR = 0xC2 After Instruction W = 0xD9 FSR = 0xC2 Before Instruction W = 0x17 FSR = 0xC2 After Instruction W = 0x17 FSR = 0x02 DS41140B-page 62 Preliminary 2002 Microchip Technology Inc. PIC16C432 BCF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None 01 00bb bfff ffff f,b BTFSC Syntax: Operands: Operation: Status Affected: Encoding: Description: Bit Test, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None 01 10bb bfff ffff Bit 'b' in register 'f' is cleared. 1 1 BCF FLAG_REG, 7 = = 0xC7 Before Instruction FLAG_REG After Instruction FLAG_REG If bit 'b' in register 'f' is '0', then the next instruction is skipped. If bit 'b' is '0', then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a twocycle instruction. 1 1(2) HERE FALSE TRUE BTFSC GOTO * * * FLAG,1 PROCESS_CODE Words: 0x47 Cycles: Example BSF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None 01 01bb bfff ffff f,b Before Instruction PC = address HERE After Instruction if FLAG<1>= 0, PC = address TRUE if FLAG<1>=1, PC = address FALSE Bit 'b' in register 'f' is set. 1 1 BSF FLAG_REG, = = 7 0x0A 0x8A Before Instruction FLAG_REG After Instruction FLAG_REG 2002 Microchip Technology Inc. Preliminary DS41140B-page 63 PIC16C432 BTFSS Syntax: Operands: Operation: Status Affected: Encoding: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None 01 11bb bfff ffff Status Affected: Encoding: Description: CALL Syntax: Operands: Operation: Call Subroutine [ label ] CALL k 0 k 2047 (PC) + 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None 10 0kkk kkkk kkkk If bit 'b' in register 'f' is '1' then the next instruction is skipped. If bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a twocycle instruction. 1 1(2) HERE FALSE TRUE BTFSS GOTO * * * FLAG,1 PROCESS_CODE Words: Cycles: Example Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. 1 2 HERE CALL THERE Words: Cycles: Example Before Instruction PC = address HERE After Instruction if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE Before Instruction PC = Address HERE After Instruction PC = Address THERE TOS = Address HERE+1 CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z 00 0001 1fff ffff f The contents of register 'f' are cleared and the Z bit is set. 1 1 CLRF FLAG_REG Before Instruction FLAG_REG = 0x5A After Instruction FLAG_REG = 0x00 Z=1 DS41140B-page 64 Preliminary 2002 Microchip Technology Inc. PIC16C432 COMF CLRW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example Clear W Syntax: [ label ] CLRW None 00h (W) 1Z Z 00 0001 0000 0011 Operation: Status Affected: Encoding: Description: Operands: [ label ] COMF 0 f 127 d [0,1] (f) (dest) Z 00 1001 dfff ffff f,d Complement f W register is cleared. Zero bit (Z) is set. 1 1 CLRW Before Instruction W = 0x5A After Instruction W = 0x00 Z=1 Words: Cycles: Example The contents of register 'f' are complemented. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f'. 1 1 COMF REG1,0 Before Instruction REG1 = 0x13 After Instruction REG1 = 0x13 W = 0xEC CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD 00 0000 0110 0100 DECF Syntax: Operands: Operation: Status Affected: Encoding: Description: Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (dest) Z 00 0011 dfff ffff Status Affected: Encoding: Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. 1 1 CLRWDT Before Instruction WDT counter = ? After Instruction WDT counter = 0x00 WDT prescaler = 0 TO = 1 PD = 1 Decrement register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. 1 1 DECF CNT, 1 Words: Cycles: Example Words: Cycles: Example Before Instruction CNT = 0x01 Z=0 After Instruction CNT = 0x00 Z=1 2002 Microchip Technology Inc. Preliminary DS41140B-page 65 PIC16C432 DECFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (dest); None 00 1011 dfff ffff skip if result = 0 INCF Syntax: Operands: Operation: Status Affected: Encoding: Description: Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (dest) Z 00 1010 dfff ffff The contents of register 'f' are decremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two-cycle instruction. 1 1(2) HERE DECFSZ GOTO CONTINUE * * * CNT, 1 LOOP The contents of register 'f' are incremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'. 1 1 INCF CNT, 1 Words: Cycles: Example Words: Cycles: Example Before Instruction CNT = 0xFF Z=0 After Instruction CNT = 0x00 Z=1 Before Instruction PC = address HERE After Instruction CNT = CNT - 1 if CNT = 0, PC = address CONTINUE if CNT1/4 0, PC = address HERE+1 GOTO Syntax: Operands: Operation: Status Affected: Encoding: Description: Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None 10 1kkk kkkk kkkk GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a twocycle instruction. 1 2 GOTO THERE After Instruction PC = Address THERE Words: Cycles: Example DS41140B-page 66 Preliminary 2002 Microchip Technology Inc. PIC16C432 INCFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d IORLW Syntax: Operands: Operation: Status Affected: Encoding: 1111 dfff ffff Description: Inclusive OR Literal with W [ label ] IORLW k 0 f 127 d [0,1] (f) + 1 (dest), skip if result = 0 None 00 0 k 255 (W) .OR. k (W) Z 11 1000 kkkk kkkk The contents of register 'f' are incremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two-cycle instruction. 1 1(2) HERE 1 INCFSZ CNT, LOOP The contents of the W register are OR'ed with the eight bit literal 'k'. The result is placed in the W register. 1 1 IORL W 0x35 Words: Cycles: Example Words: Cycles: Example Before Instruction W = 0x9A After Instruction W = 0xBF Z=1 GOTO CONTINUE * * * IORWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR W with f [ label ] IORWF f,d Before Instruction PC = address HERE After Instruction CNT = CNT + 1 if CNT = 0, PC = address CONTINUE if CNT0, PC = address HERE +1 0 f 127 d [0,1] (W) .OR. (f) (dest) Z 00 0100 dfff ffff Inclusive OR the W register with register 'f'. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'. 1 1 IORWF RESULT, 0 Words: Cycles: Example Before Instruction RESULT = 0x13 W = 0x91 After Instruction RESULT = 0x13 W = 0x93 Z=1 2002 Microchip Technology Inc. Preliminary DS41140B-page 67 PIC16C432 MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Move Literal to W [ label ] k (W) None 11 00xx kkkk kkkk MOVLW k MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example 0x5A Move W to f [ label ] (W) (f) None 00 0000 1fff ffff MOVWF f 0 k 255 0 f 127 The eight bit literal 'k' is loaded into W register. The don't cares will assemble as 0's. 1 1 MOVLW Move data from W register to register 'f'. 1 1 MOVWF OPTION Words: Cycles: Example After Instruction W = 0x5A MOVF Syntax: Operands: Operation: Status Affected: Encoding: Description: Move f [ label ] MOVF f,d NOP Syntax: Operands: Operation: 1000 dfff ffff Status Affected: Encoding: Description: Words: Cycles: Example Before Instruction OPTION = 0xFF W = 0x4F After Instruction OPTION = 0x4F W = 0x4F 0 f 127 d [0,1] (f) (dest) Z 00 No Operation [ label ] None No operation None 00 0000 0xx0 0000 NOP The contents of register f are moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. 1 1 MOVF FSR, 0 No operation. 1 1 NOP Words: Cycles: Example After Instruction W = value in FSR register Z=1 DS41140B-page 68 Preliminary 2002 Microchip Technology Inc. PIC16C432 OPTION Syntax: Operands: Operation: Status Affected: Encoding: Description: Load Option Register [ label ] None (W) OPTION None 00 0000 0110 0010 Status Affected: Encoding: Description: The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/ writable register, the user can directly address it. 1 1 To maintain upward compatibility with future PICmicro(R) products, do not use this instruction. OPTION RETLW Syntax: Operands: Operation: Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None 11 01xx kkkk kkkk The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 1 2 CALL TABLE ;W contains table ;offset value * ;W now has table value * * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 Words: Cycles: Example Words: Cycles: Example TABLE RETFIE Syntax: Operands: Operation: Status Affected: Encoding: Description: Return from Interrupt [ label ] None TOS PC, 1 GIE None 00 0000 0000 1001 RETURN Syntax: Operands: Operation: Status Affected: Encoding: Description: RETFIE Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. 1 2 RETFIE After Interrupt PC = TOS GIE = 1 Return from Subroutine [ label ] None TOS PC None 00 0000 0000 1000 RETURN Words: Cycles: Example Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. 1 2 RETURN After Interrupt PC = TOS Words: Cycles: Example 2002 Microchip Technology Inc. Preliminary DS41140B-page 69 PIC16C432 RLF Syntax: Operands: Operation: Status Affected: Encoding: Description: Rotate Left f through Carry [ label ] 0 f 127 d [0,1] See description below C 00 1101 dfff ffff RLF f,d RRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C 00 1100 dfff ffff The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is stored back in register 'f'. C Register f The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'. C Register f Words: Cycles: Example 1 1 RLF REG1,0 Words: Cycles: Example 1 1 RRF REG1,0 Before Instruction REG1 = 1110 0110 C=0 After Instruction REG1 = 1110 0110 W = 1100 1100 C=1 Before Instruction REG1 = 1110 0110 C=0 After Instruction REG1 = 1110 0110 W = 0111 0011 C=0 SLEEP Syntax: Operands: Operation: [ label ] None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD 00 0000 0110 0011 SLEEP Status Affected: Encoding: Description: The power-down status bit, PD is cleared. Timeout status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See Section 9.8 for more details. 1 1 SLEEP Words: Cycles: Example: DS41140B-page 70 Preliminary 2002 Microchip Technology Inc. PIC16C432 SUBLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Subtract W from Literal [ label ] SUBLW k SUBWF Syntax: Operands: Operation: 110x kkkk kkkk Status Affected: Encoding: Description: Subtract W from f [ label ] 0 f 127 d [0,1] (f) - (W) (dest) C, DC, Z 00 0010 dfff ffff SUBWF f,d 0 k 255 k - (W) (W) C, DC, Z 11 The W register is subtracted (2's complement method) from the eight bit literal 'k'. The result is placed in the W register. 1 1 SUBLW 0x02 Words: Cycles: Example 1: Subtract (2's complement method) W register from register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. 1 1 SUBWF REG1,1 Words: Cycles: Example 1: Before Instruction W C = = 1 ? Before Instruction REG1 = W = C = After Instruction REG1 W C Example 2: = = = 1 2 1; result is positive 3 2 ? After Instruction W C Example 2: = = 1 1; result is positive Before Instruction W C = = 2 ? After Instruction W C Example 3: = = 0 1; result is zero Before Instruction REG1 = W = C = After Instruction REG1 = W = C = 0 2 1; result is zero 2 2 ? Before Instruction W C = = 3 ? After Instruction W C = = 0xFF 0; result is negative Example 3: Before Instruction REG1 = W = C = After Instruction REG1 = W = C = 0xFF 2 0; result is negative 1 2 ? 2002 Microchip Technology Inc. Preliminary DS41140B-page 71 PIC16C432 SWAPF Syntax: Operands: Operation: Status Affected: Encoding: Description: Swap Nibbles in f [ label ] 0 f 127 d [0,1] (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) None 00 1110 dfff ffff SWAPF f,d XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Exclusive OR Literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k (W) Z 11 1010 kkkk kkkk The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0, the result is placed in W register. If 'd' is 1, the result is placed in register 'f'. 1 1 SWAPF REG, 0 The contents of the W register are XOR'ed with the eight bit literal 'k'. The result is placed in the W register. 1 1 XORL W 0xAF Words: Cycles: Example: Words: Cycles: Example Before Instruction W = 0xB5 After Instruction W = 0x1A Before Instruction REG1 = 0xA5 After Instruction REG1 = 0xA5 W = 0x5A TRIS Syntax: Operands: Operation: Status Affected: Encoding: Description: Load TRIS Register [ label ] 5f7 (W) TRIS register f; None 00 0000 0110 0fff The instruction is supported for code compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly address them. 1 1 To maintain upward compatibility with future PICmicro(R) products, do not use this instruction. TRIS f XORWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Exclusive OR W with f [ label ] 0 f 127 d [0,1] (W) .XOR. (f) (dest) Z 00 0110 dfff ffff XORWF f,d Words: Cycles: Example Exclusive OR the contents of the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. 1 1 XORW F REG 1 Words: Cycles: Example Before Instruction REG = 0xAF W = 0xB5 After Instruction REG = 0x1A W = 0xB5 DS41140B-page 72 Preliminary 2002 Microchip Technology Inc. PIC16C432 11.0 DEVELOPMENT SUPPORT The MPLAB IDE allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) * Debug using: - source files - absolute listing file - machine code The ability to use MPLAB IDE with multiple debugging tools allows users to easily switch from the costeffective simulator to a full-featured emulator with minimal retraining. The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - ICEPICTM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD * Device Programmers - PRO MATE(R) II Universal Device Programmer - PICSTART(R) Plus Entry-Level Development Programmer * Low Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM 2 Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 17 Demonstration Board - KEELOQ(R) Demonstration Board 11.2 MPASM Assembler The MPASM assembler is a full-featured universal macro assembler for all PICmicro MCU's. The MPASM assembler has a command line interface and a Windows shell. It can be used as a stand-alone application on a Windows 3.x or greater system, or it can be used through MPLAB IDE. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, an absolute LST file that contains source lines and generated machine code, and a COD file for debugging. The MPASM assembler features include: * Integration into MPLAB IDE projects. * User-defined macros to streamline assembly code. * Conditional assembly for multi-purpose source files. * Directives that allow complete control over the assembly process. 11.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8-bit microcontroller market. The MPLAB IDE is a Windows(R)-based application that contains: * An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) * A full-featured editor * A project manager * Customizable toolbar and key mapping * A status bar * On-line help 11.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI `C' compilers for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compilers provide symbol information that is compatible with the MPLAB IDE memory display. 2002 Microchip Technology Inc. Preliminary DS41140B-page 73 PIC16C432 11.4 MPLINK Object Linker/ MPLIB Object Librarian 11.6 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker. When a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The MPLIB object librarian manages the creation and modification of library files. The MPLINK object linker features include: * Integration with MPASM assembler and MPLAB C17 and MPLAB C18 C compilers. * Allows all memory areas to be defined as sections to provide link-time flexibility. The MPLIB object librarian features include: * Easier linking because single libraries can be included instead of many smaller files. * Helps keep code maintainable by grouping related modules together. * Allows libraries to be created and modules to be added, listed, replaced, deleted or extracted. The MPLAB ICE universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment (IDE), which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. The PC platform and Microsoft(R) Windows environment were chosen to best make these features available to you, the end user. 11.7 ICEPIC In-Circuit Emulator 11.5 MPLAB SIM Software Simulator The MPLAB SIM software simulator allows code development in a PC-hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. The execution can be performed in single step, execute until break, or Trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and the MPLAB C18 C compilers and the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multiproject software development tool. The ICEPIC low cost, in-circuit emulator is a solution for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit OneTime-Programmable (OTP) microcontrollers. The modular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of interchangeable personality modules, or daughter boards. The emulator is capable of emulating without target application circuitry being present. DS41140B-page 74 Preliminary 2002 Microchip Technology Inc. PIC16C432 11.8 MPLAB ICD In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PICmicro MCUs and can be used to develop for this and other PICmicro microcontrollers. The MPLAB ICD utilizes the in-circuit debugging capability built into the FLASH devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM protocol, offers cost-effective in-circuit FLASH debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. Running at full speed enables testing hardware in realtime. 11.11 PICDEM 1 Low Cost PICmicro Demonstration Board The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The user can program the sample microcontrollers provided with the PICDEM 1 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The user can also connect the PICDEM 1 demonstration board to the MPLAB ICE incircuit emulator and download the firmware to the emulator for testing. A prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs connected to PORTB. 11.9 PRO MATE II Universal Device Programmer The PRO MATE II universal device programmer is a full-featured programmer, capable of operating in Stand-alone mode, as well as PC-hosted mode. The PRO MATE II device programmer is CE compliant. The PRO MATE II device programmer has programmable VDD and VPP supplies, which allow it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In Stand-alone mode, the PRO MATE II device programmer can read, verify, or program PICmicro devices. It can also set code protection in this mode. 11.12 PICDEM 2 Low Cost PIC16CXX Demonstration Board The PICDEM 2 demonstration board is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 2 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a serial EEPROM to demonstrate usage of the I2CTM bus and separate headers for connection to an LCD module and a keypad. 11.10 PICSTART Plus Entry Level Development Programmer The PICSTART Plus development programmer is an easy-to-use, low cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports all PICmicro devices with up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant. 2002 Microchip Technology Inc. Preliminary DS41140B-page 75 PIC16C432 11.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 3 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer with an adapter socket, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 3 demonstration board to test firmware. A prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM 3 demonstration board is a LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM 3 demonstration board provides an additional RS-232 interface and Windows software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals. 11.14 PICDEM 17 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. All necessary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is included and the user may erase it and program it with the other sample programs using the PRO MATE II device programmer, or the PICSTART Plus development programmer, and easily debug and test the sample code. In addition, the PICDEM 17 demonstration board supports downloading of programs to and executing out of external FLASH memory on board. The PICDEM 17 demonstration board is also usable with the MPLAB ICE in-circuit emulator, or the PICMASTER emulator and all of the sample programs can be run and modified using either emulator. Additionally, a generous prototype area is available for user hardware. 11.15 KEELOQ Evaluation and Programming Tools KEELOQ evaluation and programming tools support Microchip's HCS Secure Data Products. The HCS evaluation kit includes a LCD display to show changing codes, a decoder to decode transmissions and a programming interface to program test transmitters. DS41140B-page 76 Preliminary 2002 Microchip Technology Inc. 24CXX/ 25CXX/ 93CXX PIC14000 HCSXXX PIC16C5X PIC16C6X PIC16C7X PIC16C8X PIC17C4X PIC16F62X PIC16C7XX PIC16F8XX PIC16C9XX PIC17C7XX PIC18CXX2 PIC12CXXX PIC16CXXX PIC18FXXX MCRFXXX MCP2510 TABLE 11-1: MPLAB(R) Integrated Development Environment 9 9 9 9 9 9 9 9 9 9 9 9 9 99 99 MPLAB(R) C17 C Compiler Software Tools MPLAB(R) C18 C Compiler MPASMTM Assembler/ MPLINKTM Object Linker 9 9 Programmers Debugger Emulators Demo Boards and Eval Kits 2002 Microchip Technology Inc. 999 999 99 ** 99 99 99 99 99 99 99 99 99 99 99 99 MPLAB(R) ICE In-Circuit Emulator ICEPICTM In-Circuit Emulator 9 * * 9 9 9 9 9 9 9 MPLAB(R) ICD In-Circuit Debugger 9 ** 9 9 9 PICSTART(R) Plus Entry Level Development Programmer 9 ** 9 9 9 9 9 9 9 9 9 9 9 9 9 9 PRO MATE(R) II Universal Device Programmer 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 DEVELOPMENT TOOLS FROM MICROCHIP Preliminary 9 9 9 9 9 PICDEMTM 1 Demonstration Board PICDEMTM 2 Demonstration Board 9 9 9 9 PICDEMTM 3 Demonstration Board 9 PICDEMTM 14A Demonstration Board 9 PICDEMTM 17 Demonstration Board 9 KEELOQ(R) Evaluation Kit 99 KEELOQ(R) Transponder Kit microIDTM Programmer's Kit 99 125 kHz microIDTM Developer's Kit 125 kHz Anticollision microIDTM Developer's Kit 9 13.56 MHz Anticollision microIDTM Developer's Kit 9 MCP2510 CAN Developer's Kit PIC16C432 9 DS41140B-page 77 * Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB(R) ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77. ** Contact Microchip Technology Inc. for availability date. PIC16C432 NOTES: DS41140B-page 78 Preliminary 2002 Microchip Technology Inc. PIC16C432 12.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Ambient Temperature under bias ............................................................................................................-40 to +125C Storage Temperature ..............................................................................................................................-65 to +150C Voltage on any pin with respect to VSS (except VDD and MCLR) ....................................................-0.6V to VDD +0.6V Voltage on VDD with respect to VSS ............................................................................................................. 0 to +7.0V Voltage on RA4 with respect to VSS........................................................................................................................ 8.5V Voltage on MCLR with respect to VSS (Note 2) ..............................................................................................0 to +14V Voltage on RA4 with respect to VSS........................................................................................................................ 8.5V Voltage on LIN with respect to VSS .......................................................................................................................... 40V Total power Dissipation (Note 1)........................................................................................................................... 1.0 W Maximum Current out of VSS pin ....................................................................................................................... 300 mA Maximum Current into VDD pin .......................................................................................................................... 250 mA Input clamp current by LIN pin, IIK (VI <0 or VI > VBAT...................................................................................... 200 mA Output clamp current by LIN pin, IOK (VO <0 or VO > VBAT) ............................................................................. 200 mA Input Clamp Current, IIK (VI <0 or VI> VDD) ...................................................................................................................20 mA Output Clamp Current, IOK (VO <0 or VO>VDD).............................................................................................................20 mA Maximum Output Current sunk by any I/O pin (source by VDD) .......................................................................... 25 mA Maximum Current sourced by any I/O pin (source by VDD) ................................................................................. 25 mA Maximum Current sunk by PORTA and PORTB (source by VDD) ..................................................................... 200 mA Maximum Current sourced by PORTA and PORTB (source by VDD) ................................................................ 200 mA Maximum Current sunk by LIN pin (source by VBAT)......................................................................................... 200 mA Maximum Current sunk by BACT pin (source by VBAT)...................................................................................... 1.8 mA Note 1: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latchup. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin, rather than pulling this pin directly to VSS. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2002 Microchip Technology Inc. Preliminary DS41140B-page 79 PIC16C432 FIGURE 12-1: 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 FREQUENCY (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. 20 25 PIC16C432 VOLTAGE-FREQUENCY GRAPH, -40C TA +125C DS41140B-page 80 Preliminary 2002 Microchip Technology Inc. PIC16C432 12.1 DC CHARACTERISTICS: PIC16C432 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and -40C TA +125C for extended Characteristic Supply Voltage Battery Supply Voltage RAM Data Retention Voltage(1) VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset Brown-out Detect Voltage Supply Current(2), (4) -- -- -- IPD D020 Power-down Current(3) -- -- -- IDD-LIN IWDT DC CHARACTERISTICS Param No. D001 D001A D002 D003 D004 D005 D010 Sym VDD VBAT VDR VPOR SVDD VBOR IDD Min 4.5 8.0 -- -- 0.05* 3.7 Typ Max Units -- 13.8 1.5* VSS -- 4.0 1.2 4.0 4.0 5.5 18 -- -- -- 4.35 2.0 6.0 7.0 V V V V Conditions See Figure 12-1 through Figure 12-3 Device in SLEEP mode See section on Power-on Reset for details V/ms See section on Power-on Reset for details V mA mA mA BOREN configuration bit is cleared FOSC = 4 MHz, VDD = 5.5V, WDT disabled, XT Osc mode,(4)* FOSC = 20 MHz, VDD = 4.5V, WDT disabled, HS Osc mode FOSC = 20 MHz, VDD = 5.5V, WDT disabled*, HS Osc mode VDD = 4.5V* VDD = 5.5V VDD = 5.5V Extended LIN XCVR enabled VDD = 4.0V (125C) BOD enabled, VDD = 5.0V VDD = 4.0V VDD = 4.0V -- -- -- 5.0 9.0 15 1 A A A D313 D022 D022A D023 D023A * LIN Transceiver Current(5) WDT Current(5) -- 6.0 75 30 80 mA A A A A A 10 12 125 60 135 IBOR ICOMP IVREF Brown-out Reset Current(5) Comparator Current for each Comparator(5) VREF Current(5) -- -- -- These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. 5: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 6: Commercial temperature range only. 2002 Microchip Technology Inc. Preliminary DS41140B-page 81 PIC16C432 12.2 DC CHARACTERISTICS: PIC16C432 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and -40C TA +125C for extended Operating voltage VDD range as described in DC spec Table 12.3 Characteristic Input Low Voltage I/O ports with TTL buffer Min Typ Max Unit Conditions DC CHARACTERISTICS Parm No. Sym VIL D030 D031 D032 D033 D034 VSS VSS VSS VSS VSS -8 -- D040 with Schmitt Trigger input MCLR, RA4/T0CKI,OSC1 (in RC mode) OSC1 (in XT and HS) OSC1 (in LP) VIL_LIN Low level input voltage VIH Input High Voltage I/O ports with TTL buffer -- -- -- -- 0.8V 0.15 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.6 VDD - 1.0 0.4 VBAT V V V V V V VDD = 4.5V to 5.5V, Otherwise (Note 1) Dominant State D041 with Schmitt Trigger input D042 MCLR RA4/T0CKI D043 OSC1 (XT, HS and LP) D043A OSC1 (in RC mode) D044 VIH_LIN High level input voltage D070 IPURB PORTB weak pull-up current IIL D060 D061 D063 D064 D080 D083 D084 D085 Input Leakage Current(2), (3) I/O ports (Except PORTA) PORTA RA4/T0CKI OSC1, MCLR IOH_LIN High level output leakage current VOL Output Low Voltage I/O ports OSC2/CLKOUT (RC only) BACT VOL_LIN Low level output voltage VOH D090 D092 Output High Voltage(3) I/O ports (Except RA4) OSC2/CLKOUT (RC only) 2.0V .25 VDD + 0.8V 0.8 VDD 0.8 VDD 0.7 VDD 0.9 VDD 0.6 VBAT 50 -- -- -- -- 200 VDD VDD VDD VDD VDD 18 400 1.0 0.5 1.0 5.0 20 0.6 0.6 0.6 0.6 TBD 0.2 VBAT V VDD = 4.5V to 5.5V V V V A A A A A A (Note 1) Recessive State VDD = 5.0V, VPIN = VSS VSS VPIN VDD, pin at hi-impedance Vss VPIN VDD, pin at hi-impedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc configuration VBUS VBAT; VBUS < 40V IOL=8.5 mA, VDD=4.5V, -40 to +85C IOL=7.0 mA, VDD=4.5V, +125C IOL=1.6 mA, VDD=4.5V, -40 to +85C IOL=1.2 mA, VDD=4.5V, +125C TBD IOL = 200 mA VBUS = 12V IOH=-3.0 mA, VDD=4.5V, -40 to +85C IOH=-2.5 mA, VDD=4.5V, +125C IOH=-1.3 mA, VDD=4.5V, -40 to +85C IOH=-1.0 mA, VDD=4.5V, +125C VBAT = 18V, VDD = 5.0V, IOH = 1.8 mA RA4 pin -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V V V V V D093 VOH BACT D094 VOH_LIN High level output voltage D150* VOD Open-Drain High Voltage * These parameters are characterized but not tested. VDD-0.7 VDD-0.7 VDD-0.7 VDD-0.7 4.0V 0.8 VBAT -- -- -- -- -- -- -- -- -- -- -- 8.5 V V V V V V V Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C432 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: LIN tested 4 MHz, 14.4V VBAT, 5.0V VDD. DS41140B-page 82 Preliminary 2002 Microchip Technology Inc. PIC16C432 12.2 DC CHARACTERISTICS: PIC16C432 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and -40C TA +125C for extended Operating voltage VDD range as described in DC spec Table 12.3 Characteristic Min Typ Max Unit Conditions DC CHARACTERISTICS Parm No. Sym D100 100A 100B D101 Capacitive Loading Specs on Output Pins COSC2 OSC2 pin CLIN LIN(4) CBACT BACT CIO All I/O pins/OSC2 (in RC mode) * These parameters are characterized but not tested. 15* 10* 50* 50* pF nF pF pF In XT, HS and LP modes when external clock used to drive OSC1 Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C432 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: LIN tested 4 MHz, 14.4V VBAT, 5.0V VDD. 12.3 LIN Transceiver Bus Interface Specifications Operating Conditions: VDD range as described in Table 12-1, -40C 2002 Microchip Technology Inc. Preliminary DS41140B-page 83 PIC16C432 12.4 Comparator Specifications Operating Conditions: VDD range as described in Table 12-1, -40C Sym VIOFF VICM CMRR TRESP Characteristics Input Offset Voltage Input Common Mode Voltage CMRR Response Time(1) Min Typ 5.0 Max 10 VDD - 1.5 Units mV V db ns s Comments 0 +55* 150* 400* 10* TMC2OV Comparator Mode Change to Output Valid These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD. 12.5 Voltage Reference Specifications. Operating Conditions: VDD range as described in Table 12-1, -40C Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111. 12.6 LIN Transceiver Operating Specifications. Operating Conditions: VDD range as described in Table 12-1, -40C DS41140B-page 84 Preliminary 2002 Microchip Technology Inc. PIC16C432 12.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase subscripts (pp) and their meanings: pp ck CLKOUT io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low T Time osc t0 OSC1 T0CKI P R V Z Period Rise Valid Hi-Impedance FIGURE 12-2: LOAD CONDITIONS Load condition 1 VDD/2 Load condition 2 RL Pin VSS RL = 464 CL = 50 pF 15 pF 10 nF CL Pin VSS CL for all pins except OSC2 and LIN bus for OSC2 output for LIN 2002 Microchip Technology Inc. Preliminary DS41140B-page 85 PIC16C432 12.8 Timing Diagrams and Specifications EXTERNAL CLOCK TIMING Q4 OSC1 1 2 CLKOUT 3 3 4 4 Q1 Q2 Q3 Q4 Q1 FIGURE 12-3: TABLE 12-1: Param No. 1A Sym Fosc EXTERNAL CLOCK TIMING REQUIREMENTS Characteristic External CLKIN Frequency(1) Min DC DC DC Oscillator Frequency (1) Typ -- -- -- -- -- -- - -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 4 20 200 4 4 20 200 -- -- -- -- 10,000 1,000 -- DC -- -- -- -- -- -- Units MHz MHz kHz MHz MHz MHz kHz ns ns ms ns ns ns ms ns ns ms ns ns ns ns Conditions XT and RC Osc mode, VDD=5.0V HS Osc mode LP Osc mode RC Osc mode, VDD=5.0 OV XT Osc mode HS Osc mode LP Osc mode XT and RC Osc mode HS Osc mode LP Osc mode RC Osc mode XT Osc mode HS Osc mode LP Osc mode TCY=FOSC/4 XT oscillator, TOSC L/H duty cycle LP oscillator, TOSC L/H duty cycle HS oscillator, TOSC L/H duty cycle XT oscillator LP oscillator HS oscillator DC 0.1 1 DC 1 Tosc External CLKIN Period(1) 250 50 5 Oscillator Period(1) 250 250 50 5 2 3* Tcy TosL, TosH TosR, TosF Instruction Cycle Time(1) External Clock in (OSC1) High or Low Time External Clock in (OSC1) Rise or Fall Time 200 100* 2* 20* 25* 50* 15* 4* * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. characterization data for that particular oscillator type, under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on DS41140B-page 86 Preliminary 2002 Microchip Technology Inc. PIC16C432 FIGURE 12-4: CLKOUT AND I/O TIMING Q4 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) Old Value 15 New Value 19 22 23 18 12 16 11 Q1 Q2 Q3 20, 21 Note 1: All tests must be done with specified capacitance loads (Figure 12-2) 50 pF on I/O pins and CLKOUT. TABLE 12-2: Param No. 10* 11* 12* 13* 14* 15* 16* 17* 18* 19* 20* 21* 22* 23 * CLKOUT AND I/O TIMING REQUIREMENTS Sym Characteristic Min -- -- -- -- -- TOSC +200 ns 0 -- 100 0 -- -- 25 TCY Typ 75 75 35 35 -- -- -- 50 -- -- 10 10 -- -- Max 200 200 100 100 20 -- -- 150 -- -- 40 40 -- -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns TosH2ckL OSC1 to CLKOUT (1) TosH2ckH OSC1 to CLKOUT (1) TckR TckF TckL2ioV CLKOUT rise time(1) CLKOUT fall time(1) CLKOUT to Port out valid(1) Port in hold after CLKOUT (1) OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port output rise time Port output fall time RB0/INT pin high or low time RB<7:4> change interrupt high or low time TioV2ckH Port in valid before CLKOUT (1) TckH2ioI TosH2ioI TosH2ioV OSC1 (Q1 cycle) to Port out valid TioV2osH Port input valid to OSC1 (I/O in setup time) TioR TioF Tinp Trbp These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. 2002 Microchip Technology Inc. Preliminary DS41140B-page 87 PIC16C432 FIGURE 12-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR Internal POR 33 PWRT Timeout OSC Timeout Internal RESET Watchdog Timer Reset 34 I/O Pins 32 30 31 34 FIGURE 12-6: BROWN-OUT RESET TIMING VDD BVDD 35 TABLE 12-3: Param No. 30 31 32 33 34 35 * Sym TmcL Twdt Tost Tpwrt TIOZ TBOR RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Characteristic MCLR Pulse Width (low) Watchdog Timer Timeout Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O hi-impedance from MCLR low Brown-out Reset Pulse Width 100* Min 2000 7* -- 28* Typ -- 18 1024 TOSC 72 -- -- Max -- 33* -- 132* 2.0 -- Units ns ms -- ms ms ms 3.7V VDD 4.3V Conditions -40 to +85C VDD = 5.0V, -40 to +85C TOSC = OSC1 period VDD = 5.0V, -40 to +85C These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS41140B-page 88 Preliminary 2002 Microchip Technology Inc. PIC16C432 FIGURE 12-7: RA4/T0CKI TIMER0 CLOCK TIMING 40 42 41 TMR0 TABLE 12-4: Parameter No. 40 TIMER0 CLOCK REQUIREMENTS Characteristic No Prescaler With Prescaler Min 0.5 TCY + 20* 10* 0.5 TCY + 20* 10* TCY + 40* N Typ -- -- -- -- -- Max -- -- -- -- -- Units ns ns ns ns ns N = prescale value (1, 2, 4, ..., 256) Conditions Sym Tt0H T0CKI High Pulse Width 41 Tt0L T0CKI Low Pulse Width No Prescaler With Prescaler 42 * Tt0P T0CKI Period These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 12-5: Symbol dV/dt Ttrans_pd Trec_pd Trec_sym LIN AC CHARACTERISTICS Parameter Min. 1 Typ. 2 Max. 3 4 6 -2 2 Unit V/s s s s (Note 1) Ttrans_pd= max(Ttrans_pdr or Ttrans_pdf) Trec_pd = max (Trec_pdr or Trec_pdf) Trec_sym = Trec_pdf - Trec_pdr Note Slope rising and falling edges Propagation delay of transmitter Propagation delay of receiver Symmetry of receiver propagation delay rising edge w.r.t. falling edge Ttrans_sym Symmetry of transmitter propagation delay rising edge w.r.t. falling edge -2 2 s Ttrans_sym = Ttrans_pdf - Trans_pdr Note 1: Rising edge is system dependent. Value is characterized but not tested. 2002 Microchip Technology Inc. Preliminary DS41140B-page 89 PIC16C432 TABLE 12-6: Symbol recovery shutdown TTHERM LIN THERMAL CHARACTERISTICS Parameter Recovery Temperature Shutdown Temperature Thermal Recovery Time Typ. +135 +155 1.5 Max. Unit C C ms Note Information Parameter Information Parameter Information Parameter FIGURE 12-8: TIMING DIAGRAM TxD (input of physical layer) t trans_pdf t trans_pdr Bus Signal rec. threshold rec. threshold t rec_pdf t rec_pdr RxD (physical layer output) DS41140B-page 90 Preliminary 2002 Microchip Technology Inc. PIC16C432 13.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs and tables, the data presented is outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. `Typical' represents the mean of the distribution at 25C. `max' or `min' represents (mean + 3) or (mean - 3) respectively, where is standard deviation, over the whole temperature range. FIGURE 13-1: 20 18 16 14 VLIN (V) 12 10 8 6 4 2 LIN TRANSCEIVER SHUTDOWN HYSTERESIS (V) VS. TEMPERATURE (C) 135.2 143.1 150.0 VBAT = 18.0V VDD = 5.0V TXD = 0V Temp (Shutdown) Temp (Recover) 120 0 115 120 125 130 135.2 135 140 143.1 145 150 155 TEMPERATURE (C) 2002 Microchip Technology Inc. Preliminary DS41140B-page 91 PIC16C432 NOTES: DS41140B-page 92 Preliminary 2002 Microchip Technology Inc. PIC16C432 14.0 14.1 PACKAGING INFORMATION Package Marking Information 20-Lead CERDIP Windowed XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example PIC16C432/P301 0007CBP 20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Example PIC16C432 -I/218 0007CBP 20-Lead PDIP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example PIC16C432/P301 0007CBP Legend: XX...X YY WW NNN Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, and traceability code. For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2002 Microchip Technology Inc. Preliminary DS41140B-page 93 PIC16C432 20-Lead Ceramic Dual In-Line with Window (JW) - 300 mil (CERDIP) Package drawing not available at this time. DS41140B-page 94 Preliminary 2002 Microchip Technology Inc. PIC16C432 20-Lead Plastic Shrink Small Outline (SS) - 209 mil, 5.30 mm (SSOP) E E1 p D B n 2 1 a c A A2 f L b A1 Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D L c f B a b MIN .068 .064 .002 .299 .201 .278 .022 .004 0 .010 0 0 INCHES* NOM 20 .026 .073 .068 .006 .309 .207 .284 .030 .007 4 .013 5 5 MAX MIN .078 .072 .010 .322 .212 .289 .037 .010 8 .015 10 10 MILLIMETERS NOM 20 0.65 1.73 1.85 1.63 1.73 0.05 0.15 7.59 7.85 5.11 5.25 7.06 7.20 0.56 0.75 0.10 0.18 0.00 101.60 0.25 0.32 0 5 0 5 MAX 1.98 1.83 0.25 8.18 5.38 7.34 0.94 0.25 203.20 0.38 10 10 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072 2002 Microchip Technology Inc. Preliminary DS41140B-page 95 PIC16C432 20-Lead Plastic Dual In-Line (P) - 300 mil (PDIP) E1 D 2 n E 1 A A2 c A1 L B1 eB Units Dimension Limits n p B INCHES* NOM 20 .100 .155 .130 p MILLIMETERS NOM 20 2.54 3.56 3.94 2.92 3.30 0.38 7.49 7.87 6.10 6.35 26.04 26.24 3.05 3.30 0.20 0.29 1.40 1.52 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX MIN MAX Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .295 .310 .325 Molded Package Width .240 .250 .260 E1 Overall Length D 1.025 1.033 1.040 Tip to Seating Plane L .120 .130 .140 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .055 .060 .065 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .310 .370 .430 5 10 15 Mold Draft Angle Top Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-019 4.32 3.68 8.26 6.60 26.42 3.56 0.38 1.65 0.56 10.92 15 15 DS41140B-page 96 Preliminary 2002 Microchip Technology Inc. PIC16C432 APPENDIX A: CODE FOR LIN COMMUNICATION Please check our web site at www.microchip.com for code availability. 2002 Microchip Technology Inc. Preliminary DS41140B-page 97 PIC16C432 NOTES: DS41140B-page 98 Preliminary 2002 Microchip Technology Inc. PIC16C432 INDEX A ADDLW Instruction ............................................................. 62 ADDWF Instruction ............................................................. 62 ANDLW Instruction ............................................................. 62 ANDWF Instruction ............................................................. 62 Assembler MPASM Assembler ..................................................... 73 BCF ............................................................................ 63 BSF............................................................................. 63 BTFSC........................................................................ 63 BTFSS ........................................................................ 64 CALL........................................................................... 64 CLRF .......................................................................... 64 CLRW ......................................................................... 65 CLRWDT .................................................................... 65 COMF ......................................................................... 65 DECF.......................................................................... 65 DECFSZ ..................................................................... 66 GOTO ......................................................................... 66 INCF ........................................................................... 66 INCFSZ....................................................................... 67 IORLW ........................................................................ 67 IORWF........................................................................ 67 MOVF ......................................................................... 68 MOVLW ...................................................................... 68 MOVWF...................................................................... 68 NOP............................................................................ 68 OPTION ...................................................................... 69 RETFIE....................................................................... 69 RETLW ....................................................................... 69 RETURN..................................................................... 69 RLF............................................................................. 70 RRF ............................................................................ 70 SLEEP ........................................................................ 70 SUBLW ....................................................................... 71 SUBWF....................................................................... 71 SWAPF ....................................................................... 72 TRIS ........................................................................... 72 XORLW....................................................................... 72 XORWF ...................................................................... 72 Instruction Set Summary .................................................... 59 INT Interrupt ....................................................................... 54 INTCON Register................................................................ 12 Interrupts ............................................................................ 53 IORLW Instruction .............................................................. 67 IORWF Instruction .............................................................. 67 B BCF Instruction ................................................................... 63 Block Diagram TIMER0....................................................................... 27 TMR0/WDT PRESCALER .......................................... 30 Brown-out Detect (BOD) ..................................................... 48 BSF Instruction ................................................................... 63 BTFSC Instruction............................................................... 63 BTFSS Instruction ............................................................... 64 C CALL Instruction ................................................................. 64 CLRF Instruction ................................................................. 64 CLRW Instruction ................................................................ 65 CLRWDT Instruction ........................................................... 65 CMCON Register ................................................................ 33 Code Protection .................................................................. 58 COMF Instruction ................................................................ 65 Comparator Configuration................................................... 33 Comparator Interrupts ......................................................... 39 Comparator Module ............................................................ 33 Comparator Operation ........................................................ 35 Comparator Reference ....................................................... 35 Configuration Bits................................................................ 43 Configuring the Voltage Reference ..................................... 41 Crystal Operation ................................................................ 45 D Data Memory Organization ................................................... 7 DECF Instruction................................................................. 65 DECFSZ Instruction ............................................................ 66 Development Support ......................................................... 73 K KEELOQ Evaluation and Programming Tools...................... 76 E Errata .................................................................................... 2 External Crystal Oscillator Circuit ....................................... 46 L LIN Hardware Interface....................................................... 23 LIN Interfacing .................................................................... 23 LIN Protocol ........................................................................ 23 LIN Transceiver .................................................................. 23 G General Purpose Register File.............................................. 7 GOTO Instruction ................................................................ 66 M MOVF Instruction................................................................ 68 MOVLW Instruction............................................................. 68 MOVWF Instruction ............................................................ 68 MPLAB C17 and MPLAB C18 C Compilers ....................... 73 MPLAB ICD In-Circuit Debugger ........................................ 75 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE ................................................................. 74 MPLAB Integrated Development Environment Software.... 73 MPLINK Object Linker/MPLIB Object Librarian .................. 74 I I/O Ports .............................................................................. 17 I/O Programming Considerations........................................ 22 ICEPIC In-Circuit Emulator ................................................. 74 ID Locations ........................................................................ 58 INCF Instruction .................................................................. 66 INCFSZ Instruction ............................................................. 67 In-Circuit Serial Programming ............................................. 58 Indirect Addressing, INDF and FSR Registers ................... 16 Instruction Set ADDLW ....................................................................... 62 ADDWF....................................................................... 62 ANDLW ....................................................................... 62 ANDWF....................................................................... 62 N NOP Instruction .................................................................. 68 O One-Time-Programmable (OTP) Devices ............................ 5 2002 Microchip Technology Inc. Preliminary DS41140B-page 99 PIC16C432 OPTION Instruction............................................................. 69 OPTION Register ................................................................ 11 Oscillator Configurations ..................................................... 45 Oscillator Start-up Timer (OST) .......................................... 48 Switching Prescaler Assignment ................................ 31 Timing Diagrams and Specifications .................................. 86 TMR0 Interrupt.................................................................... 54 TRIS Instruction .................................................................. 72 TRISA ................................................................................. 17 TRISB ................................................................................. 20 P Package Marking Information ............................................. 93 Packaging Information ........................................................ 93 PCL and PCLATH ............................................................... 15 PCON Register ................................................................... 14 PICDEM 1 Low Cost PICmicro Demonstration Board ........ 75 PICDEM 17 Demonstration Board ...................................... 76 PICDEM 2 Low Cost PIC16CXX Demonstration Board...... 75 PICDEM 3 Low Cost PIC16CXXX Demonstration Board ... 76 PICSTART Plus Entry Level Development Programmer .... 75 PIE1 Register ...................................................................... 13 PIR1 Register...................................................................... 13 Port RB Interrupt ................................................................. 54 PORTA................................................................................ 17 PORTB................................................................................ 20 Power Control/Status Register (PCON) .............................. 49 Power-down Mode (SLEEP) ............................................... 57 Power-on Reset (POR) ....................................................... 48 Timeout (TO Bit).......................................................... 10 Power-up Timer (PWRT)..................................................... 48 Prescaler ............................................................................. 30 Program Memory Organization ............................................. 7 V Voltage Reference Module ................................................. 41 VRCON Register ................................................................ 41 W Watchdog Timer (WDT)...................................................... 56 WWW, On-Line Support ....................................................... 2 X XORLW Instruction ............................................................. 72 XORWF Instruction............................................................. 72 Q Quick-Turn-Programming (QTP) Devices ............................. 5 R RC Oscillator ....................................................................... 46 RESET ................................................................................ 47 RETFIE Instruction.............................................................. 69 RETLW Instruction .............................................................. 69 RETURN Instruction............................................................ 69 RLF Instruction.................................................................... 70 RRF Instruction ................................................................... 70 S Serialized Quick-Turn-Programming (SQTP) Devices.......... 5 SLEEP Instruction ............................................................... 70 Software Simulator (MPLAB SIM)....................................... 74 Special Features of the CPU............................................... 43 Special Function Registers ................................................... 8 Stack ................................................................................... 15 STATUS Register DC Bit.......................................................................... 10 IRP Bit ......................................................................... 10 TO Bit .......................................................................... 10 Z Bit............................................................................. 10 Status Register.................................................................... 10 SUBLW Instruction.............................................................. 71 SUBWF Instruction.............................................................. 71 SWAPF Instruction.............................................................. 72 T Thermal Shutdown .............................................................. 23 Timer0 TIMER0 ....................................................................... 27 TIMER0 (TMR0) Interrupt ........................................... 27 TIMER0 (TMR0) Module ............................................. 27 TMR0 with External Clock........................................... 29 Timer1 DS41140B-page 100 Preliminary 2002 Microchip Technology Inc. PIC16C432 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape(R) or Microsoft(R) Internet Explorer. Files are also available for FTP download from our FTP site. SYSTEMS INFORMATION AND UPGRADE HOT LINE The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Connecting to the Microchip Internet Web Site The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events 092002 2002 Microchip Technology Inc. Preliminary DS41140B-page 101 PIC16C432 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16C432 Questions: 1. What are the best features of this document? Y N Literature Number: DS41140B FAX: (______) _________ - _________ 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41140B-page 102 Preliminary 2002 Microchip Technology Inc. PIC16C432 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples: a) PIC16C432-E/P301 = Extra Temp, PDIP package, 4 MHz, normal VDD limits, QTP pattern #301 PIC16C432-I/SS Industrial Temp., SSOP package, 4 MHz, industrial VDD limits b) Device PIC16C432: VDD range 4.0 V to 5.5 V PIC16C432T: VDD range 4.0 V to 5.5 V (Tape and Reel) Temperature Range I E = = -40C to -40C to +85C +125C Package SS = JW* = SSOP Windowed CERDIP Pattern 3-Digit Pattern Code for QTP (blank otherwise). * JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2002 Microchip Technology Inc. Preliminary DS41140B-page103 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com ASIA/PACIFIC Australia Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Japan Microchip Technology Japan K.K. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Rocky Mountain 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-4338 China - Beijing Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Atlanta 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 Boston 2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821 China - Chengdu Microchip Technology Consulting (Shanghai) Co., Ltd., Chengdu Liaison Office Rm. 2401, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599 Taiwan Microchip Technology (Barbados) Inc., Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 Chicago 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas 4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924 China - Fuzhou Microchip Technology Consulting (Shanghai) Co., Ltd., Fuzhou Liaison Office Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521 Detroit Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260 EUROPE Austria Microchip Technology Austria GmbH Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 China - Shanghai Microchip Technology Consulting (Shanghai) Co., Ltd. Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 Kokomo 2767 S. Albright Road Kokomo, Indiana 46902 Tel: 765-864-8360 Fax: 765-864-8387 Denmark Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 Los Angeles 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338 China - Shenzhen Microchip Technology Consulting (Shanghai) Co., Ltd., Shenzhen Liaison Office Rm. 1315, 13/F, Shenzhen Kerry Centre, Renminnan Lu Shenzhen 518001, China Tel: 86-755-82350361 Fax: 86-755-82366086 New York 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335 France Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 China - Hong Kong SAR Microchip Technology Hongkong Ltd. Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Germany Microchip Technology GmbH Steinheilstrasse 10 D-85737 Ismaning, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 India Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 Italy Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 08/01/02 DS41140B-page 104 Preliminary 2002 Microchip Technology Inc. |
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